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Commit MetaInfo

Révision	14566 (tree)
l'heure	2021-06-21 19:20:27
Auteur	gdisirio

Message de Log

Fixed bug #1162.

Change Summary

modified: trunk/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h (diff)
modified: trunk/os/hal/ports/STM32/STM32F3xx/stm32_registry.h (diff)
modified: trunk/readme.txt (diff)

Modification

--- trunk/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h (revision 14565)

+++ trunk/demos/STM32/RT-STM32F303-DISCOVERY/cfg/mcuconf.h (revision 14566)

		@@ -169,6 +169,19 @@
169	169	#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
170	170
171	171	/*
	172	+ * I2S driver system settings.
	173	+ */
	174	+#define STM32_I2S_USE_SPI2 FALSE
	175	+#define STM32_I2S_USE_SPI3 FALSE
	176	+#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER \| STM32_I2S_MODE_RX)
	177	+#define STM32_I2S_SPI3_MODE (STM32_I2S_MODE_MASTER \| STM32_I2S_MODE_RX)
	178	+#define STM32_I2S_SPI2_IRQ_PRIORITY 10
	179	+#define STM32_I2S_SPI3_IRQ_PRIORITY 10
	180	+#define STM32_I2S_SPI2_DMA_PRIORITY 1
	181	+#define STM32_I2S_SPI3_DMA_PRIORITY 1
	182	+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
	183	+
	184	+/*
172	185	* ICU driver system settings.
173	186	*/
174	187	#define STM32_ICU_USE_TIM1 FALSE

--- trunk/os/hal/ports/STM32/STM32F3xx/stm32_registry.h (revision 14565)

+++ trunk/os/hal/ports/STM32/STM32F3xx/stm32_registry.h (revision 14566)

		@@ -208,6 +208,8 @@
208	208	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
209	209	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
210	210	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	211	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	212	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
211	213
212	214	#define STM32_HAS_SPI3 TRUE
213	215	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -214,6 +216,8 @@
214	216	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
215	217	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
216	218	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
	219	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
	220	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
217	221
218	222	#define STM32_HAS_SPI4 FALSE
219	223	#define STM32_HAS_SPI5 FALSE

		@@ -491,6 +495,8 @@
491	495	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
492	496	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
493	497	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	498	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	499	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
494	500
495	501	#define STM32_HAS_SPI3 TRUE
496	502	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -497,6 +503,8 @@
497	503	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
498	504	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
499	505	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
	506	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
	507	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
500	508
501	509	#define STM32_HAS_SPI4 TRUE
502	510	#define STM32_SPI4_SUPPORTS_I2S FALSE

		@@ -980,6 +988,8 @@
980	988	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
981	989	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
982	990	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	991	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	992	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
983	993
984	994	#define STM32_HAS_SPI3 TRUE
985	995	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -986,6 +996,8 @@
986	996	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
987	997	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
988	998	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
	999	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
	1000	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
989	1001
990	1002	#define STM32_HAS_SPI1 FALSE
991	1003	#define STM32_HAS_SPI4 FALSE

		@@ -1209,6 +1221,8 @@
1209	1221	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
1210	1222	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
1211	1223	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	1224	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	1225	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
1212	1226
1213	1227	#define STM32_HAS_SPI3 TRUE
1214	1228	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -1215,6 +1229,8 @@
1215	1229	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
1216	1230	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
1217	1231	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
	1232	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
	1233	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
1218	1234
1219	1235	#define STM32_HAS_SPI1 FALSE
1220	1236	#define STM32_HAS_SPI4 FALSE

		@@ -1460,6 +1476,8 @@
1460	1476	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
1461	1477	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
1462	1478	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	1479	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	1480	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
1463	1481
1464	1482	#define STM32_HAS_SPI3 TRUE
1465	1483	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -1466,6 +1484,8 @@
1466	1484	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
1467	1485	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
1468	1486	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
	1487	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
	1488	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
1469	1489
1470	1490	#define STM32_HAS_SPI4 FALSE
1471	1491	#define STM32_HAS_SPI5 FALSE

		@@ -1725,6 +1745,8 @@
1725	1745	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
1726	1746	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
1727	1747	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	1748	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	1749	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
1728	1750
1729	1751	#define STM32_HAS_SPI3 TRUE
1730	1752	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -1731,6 +1753,8 @@
1731	1753	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
1732	1754	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
1733	1755	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
	1756	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
	1757	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
1734	1758
1735	1759	#define STM32_HAS_SPI4 TRUE
1736	1760	#define STM32_SPI4_SUPPORTS_I2S FALSE

		@@ -1969,6 +1993,8 @@
1969	1993	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
1970	1994	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
1971	1995	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	1996	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	1997	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
1972	1998
1973	1999	#define STM32_HAS_SPI3 TRUE
1974	2000	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -1975,6 +2001,8 @@
1975	2001	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
1976	2002	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
1977	2003	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
	2004	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
	2005	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
1978	2006
1979	2007	#define STM32_HAS_SPI1 FALSE
1980	2008	#define STM32_HAS_SPI4 FALSE

		@@ -2452,6 +2480,8 @@
2452	2480	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
2453	2481	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
2454	2482	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	2483	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	2484	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
2455	2485
2456	2486	#define STM32_HAS_SPI3 TRUE
2457	2487	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -2458,6 +2488,8 @@
2458	2488	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
2459	2489	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
2460	2490	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
	2491	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
	2492	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
2461	2493
2462	2494	#define STM32_HAS_SPI4 FALSE
2463	2495	#define STM32_HAS_SPI5 FALSE

		@@ -2965,6 +2997,8 @@
2965	2997	#define STM32_SPI2_I2S_FULLDUPLEX TRUE
2966	2998	#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
2967	2999	#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
	3000	+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
	3001	+#define STM32_I2C_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
2968	3002
2969	3003	#define STM32_HAS_SPI3 TRUE
2970	3004	#define STM32_SPI3_SUPPORTS_I2S TRUE

		@@ -2971,6 +3005,8 @@
2971	3005	#define STM32_SPI3_I2S_FULLDUPLEX TRUE
2972	3006	#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
2973	3007	#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
	3008	+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
	3009	+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
2974	3010
2975	3011	#define STM32_HAS_SPI4 TRUE
2976	3012	#define STM32_SPI4_SUPPORTS_I2S FALSE

--- trunk/readme.txt (revision 14565)

+++ trunk/readme.txt (revision 14566)

		@@ -74,4 +74,6 @@
74	74	*****************************************************************************
75	75
76	76	* Next *
	77	+- FIX: Fixed I2S-related definitions missing in STM32F3xx registry (bug #1162)
	78	+ (backported to 21.6.1)(backported to 20.3.4).
77	79	- FIX: Fixed AVR port broken (bug #1161)(backported to 21.6.1).

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