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Description du projet

Covered is a Verilog code coverage utility that
reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also
contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Système requise

System requirement is not defined
Information regarding Project Releases and Project Resources. Note that the information here is a quote from Freecode.com page, and the downloads themselves may not be hosted on OSDN.

2010-11-22 05:29
0.7.9

Cette version ajoute le support de la TVF analyse dumpfile, améliorations du langage, et des corrections de bugs.
This release adds support for FST dumpfile parsing, language enhancements, and bugfixes.

2010-03-25 20:21
0.7.8

Corrections de bogues et d'améliorations pour le support du langage Verilog.
Tags: Stable
Bugfixes and enhancements for Verilog language support.

2009-10-25 18:29
0.7.7

C'est une version corrige des bogues.
This is a bugfix release.

2009-08-26 20:45
0.7.6

C'est une version corrige des bogues.
Tags: Stable
This is a bugfix release.

2009-08-03 14:23
20090802

Plusieurs améliorations de performance ont été ajoutés pour le débit inline nouveau code de la couverture. Ce communiqué contient aussi des corrections pour des courses «inline».
Tags: Performance improvements
Several performance improvements were added for the new inlined code coverage flow. This release also contains bugfixes for inlined runs.

Project Resources