OSDN -- Développer et télécharger des logiciels Open Source
Traduction statut du Français translation status for fr
  • R/O
  • HTTP
  • SSH
  • HTTPS
Fork

Commit

Tags
Aucun tag

Frequently used words (click to add to your profile)

javac++androidlinuxc#windowsobjective-ccocoa誰得qtpythonphprubygameguibathyscaphec計画中(planning stage)翻訳omegatframeworktwitterdomtestvb.netdirectxゲームエンジンbtronarduinopreviewer

Commit MetaInfo

Révision75f78bb2de547d16b46ffe696861d5b6fa424f91 (tree)
l'heure2023-01-22 14:55:30
Auteurphabrics <phabrics@phab...>
Commiterphabrics

Message de Log

Added generated files so that they wouldn't be regenerated for each build in the repo.

Change Summary

Modification

--- /dev/null
+++ b/generic/bus-device-auto.c
@@ -0,0 +1,4637 @@
1+/* automatically generated by bus-device-auto.sh, do not edit! */
2+_TME_RCSID("$Id: bus-device-auto.sh,v 1.3 2009/08/29 17:52:04 fredette Exp $");
3+
4+/* this gives the number of entries that must be in a generic bus
5+ router array for a device with a bus size of 8 * (2 ^ siz_lg2)
6+ bits: */
7+#define TME_BUS_ROUTER_INIT_SIZE(siz_lg2) \
8+ TME_BUS_ROUTER_INIT_INDEX(siz_lg2, (1 << (siz_lg2)) + 1, 0)
9+
10+
11+/* the 16-bit big-endian bus master bus router: */
12+const tme_bus_lane_t tme_bus_device_router_16eb[TME_BUS_ROUTER_INIT_SIZE(TME_BUS16_LOG2)] = {
13+
14+ /* initiator maximum cycle size: 8 bits
15+ initiator address offset: 0 bits
16+ responder bus port size: 8 bits
17+ responder port least lane: D7-D0: */
18+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
19+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
20+
21+ /* initiator maximum cycle size: 8 bits
22+ initiator address offset: 0 bits
23+ responder bus port size: 8 bits
24+ responder port least lane: D15-D8: */
25+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
26+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
27+
28+ /* initiator maximum cycle size: 8 bits
29+ initiator address offset: 0 bits
30+ responder bus port size: 16 bits
31+ responder port least lane: D7-D0: */
32+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
33+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
34+
35+ /* initiator maximum cycle size: 8 bits
36+ initiator address offset: 0 bits
37+ responder bus port size: 16 bits
38+ responder port least lane: D15-D8
39+ (responder port not correctly positioned for this initiator): */
40+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
41+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
42+
43+ /* initiator maximum cycle size: 8 bits
44+ initiator address offset: 8 bits
45+ responder bus port size: 8 bits
46+ responder port least lane: D7-D0: */
47+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
48+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
49+
50+ /* initiator maximum cycle size: 8 bits
51+ initiator address offset: 8 bits
52+ responder bus port size: 8 bits
53+ responder port least lane: D15-D8: */
54+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
55+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
56+
57+ /* initiator maximum cycle size: 8 bits
58+ initiator address offset: 8 bits
59+ responder bus port size: 16 bits
60+ responder port least lane: D7-D0: */
61+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
62+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
63+
64+ /* initiator maximum cycle size: 8 bits
65+ initiator address offset: 8 bits
66+ responder bus port size: 16 bits
67+ responder port least lane: D15-D8
68+ (responder port not correctly positioned for this initiator): */
69+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
70+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
71+
72+ /* initiator maximum cycle size: 16 bits
73+ initiator address offset: 0 bits
74+ responder bus port size: 8 bits
75+ responder port least lane: D7-D0: */
76+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1),
77+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
78+
79+ /* initiator maximum cycle size: 16 bits
80+ initiator address offset: 0 bits
81+ responder bus port size: 8 bits
82+ responder port least lane: D15-D8: */
83+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
84+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
85+
86+ /* initiator maximum cycle size: 16 bits
87+ initiator address offset: 0 bits
88+ responder bus port size: 16 bits
89+ responder port least lane: D7-D0: */
90+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1),
91+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
92+
93+ /* initiator maximum cycle size: 16 bits
94+ initiator address offset: 0 bits
95+ responder bus port size: 16 bits
96+ responder port least lane: D15-D8
97+ (responder port not correctly positioned for this initiator): */
98+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
99+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
100+
101+ /* initiator maximum cycle size: 16 bits
102+ initiator address offset: 8 bits
103+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
104+ responder bus port size: 8 bits
105+ responder port least lane: D7-D0: */
106+ /* D7-D0 */ TME_BUS_LANE_ABORT,
107+ /* D15-D8 */ TME_BUS_LANE_ABORT,
108+
109+ /* initiator maximum cycle size: 16 bits
110+ initiator address offset: 8 bits
111+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
112+ responder bus port size: 8 bits
113+ responder port least lane: D15-D8: */
114+ /* D7-D0 */ TME_BUS_LANE_ABORT,
115+ /* D15-D8 */ TME_BUS_LANE_ABORT,
116+
117+ /* initiator maximum cycle size: 16 bits
118+ initiator address offset: 8 bits
119+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
120+ responder bus port size: 16 bits
121+ responder port least lane: D7-D0: */
122+ /* D7-D0 */ TME_BUS_LANE_ABORT,
123+ /* D15-D8 */ TME_BUS_LANE_ABORT,
124+
125+ /* initiator maximum cycle size: 16 bits
126+ initiator address offset: 8 bits
127+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
128+ responder bus port size: 16 bits
129+ responder port least lane: D15-D8
130+ (responder port not correctly positioned for this initiator): */
131+ /* D7-D0 */ TME_BUS_LANE_ABORT,
132+ /* D15-D8 */ TME_BUS_LANE_ABORT,
133+};
134+
135+/* the 16-bit little-endian bus master bus router: */
136+const tme_bus_lane_t tme_bus_device_router_16el[TME_BUS_ROUTER_INIT_SIZE(TME_BUS16_LOG2)] = {
137+
138+ /* initiator maximum cycle size: 8 bits
139+ initiator address offset: 0 bits
140+ responder bus port size: 8 bits
141+ responder port least lane: D7-D0: */
142+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
143+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
144+
145+ /* initiator maximum cycle size: 8 bits
146+ initiator address offset: 0 bits
147+ responder bus port size: 8 bits
148+ responder port least lane: D15-D8: */
149+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
150+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
151+
152+ /* initiator maximum cycle size: 8 bits
153+ initiator address offset: 0 bits
154+ responder bus port size: 16 bits
155+ responder port least lane: D7-D0: */
156+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
157+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
158+
159+ /* initiator maximum cycle size: 8 bits
160+ initiator address offset: 0 bits
161+ responder bus port size: 16 bits
162+ responder port least lane: D15-D8
163+ (responder port not correctly positioned for this initiator): */
164+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
165+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
166+
167+ /* initiator maximum cycle size: 8 bits
168+ initiator address offset: 8 bits
169+ responder bus port size: 8 bits
170+ responder port least lane: D7-D0: */
171+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
172+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
173+
174+ /* initiator maximum cycle size: 8 bits
175+ initiator address offset: 8 bits
176+ responder bus port size: 8 bits
177+ responder port least lane: D15-D8: */
178+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
179+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
180+
181+ /* initiator maximum cycle size: 8 bits
182+ initiator address offset: 8 bits
183+ responder bus port size: 16 bits
184+ responder port least lane: D7-D0: */
185+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
186+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
187+
188+ /* initiator maximum cycle size: 8 bits
189+ initiator address offset: 8 bits
190+ responder bus port size: 16 bits
191+ responder port least lane: D15-D8
192+ (responder port not correctly positioned for this initiator): */
193+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
194+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
195+
196+ /* initiator maximum cycle size: 16 bits
197+ initiator address offset: 0 bits
198+ responder bus port size: 8 bits
199+ responder port least lane: D7-D0: */
200+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
201+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
202+
203+ /* initiator maximum cycle size: 16 bits
204+ initiator address offset: 0 bits
205+ responder bus port size: 8 bits
206+ responder port least lane: D15-D8: */
207+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
208+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
209+
210+ /* initiator maximum cycle size: 16 bits
211+ initiator address offset: 0 bits
212+ responder bus port size: 16 bits
213+ responder port least lane: D7-D0: */
214+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
215+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
216+
217+ /* initiator maximum cycle size: 16 bits
218+ initiator address offset: 0 bits
219+ responder bus port size: 16 bits
220+ responder port least lane: D15-D8
221+ (responder port not correctly positioned for this initiator): */
222+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
223+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
224+
225+ /* initiator maximum cycle size: 16 bits
226+ initiator address offset: 8 bits
227+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
228+ responder bus port size: 8 bits
229+ responder port least lane: D7-D0: */
230+ /* D7-D0 */ TME_BUS_LANE_ABORT,
231+ /* D15-D8 */ TME_BUS_LANE_ABORT,
232+
233+ /* initiator maximum cycle size: 16 bits
234+ initiator address offset: 8 bits
235+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
236+ responder bus port size: 8 bits
237+ responder port least lane: D15-D8: */
238+ /* D7-D0 */ TME_BUS_LANE_ABORT,
239+ /* D15-D8 */ TME_BUS_LANE_ABORT,
240+
241+ /* initiator maximum cycle size: 16 bits
242+ initiator address offset: 8 bits
243+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
244+ responder bus port size: 16 bits
245+ responder port least lane: D7-D0: */
246+ /* D7-D0 */ TME_BUS_LANE_ABORT,
247+ /* D15-D8 */ TME_BUS_LANE_ABORT,
248+
249+ /* initiator maximum cycle size: 16 bits
250+ initiator address offset: 8 bits
251+ (a 16-bit initiator cannot request 16 bits at an 8-bit offset - this is an array placeholder)
252+ responder bus port size: 16 bits
253+ responder port least lane: D15-D8
254+ (responder port not correctly positioned for this initiator): */
255+ /* D7-D0 */ TME_BUS_LANE_ABORT,
256+ /* D15-D8 */ TME_BUS_LANE_ABORT,
257+};
258+
259+/* the 16-bit bus master DMA read function: */
260+int
261+tme_bus_device_dma_read_16(struct tme_bus_device *bus_device,
262+ tme_bus_addr_t address_init,
263+ tme_bus_addr_t size,
264+ tme_uint8_t *buffer,
265+ unsigned int locks)
266+{
267+ struct tme_bus_tlb *tlb, tlb_local;
268+ struct tme_bus_connection *conn_bus;
269+ tme_bus_addr_t count_minus_one, count;
270+ struct tme_bus_cycle cycle;
271+ tme_bus_addr_t address_resp;
272+ int shift;
273+ int err;
274+
275+ /* assume no error: */
276+ err = TME_OK;
277+
278+ /* loop while we have more bytes to read: */
279+ for (; err == TME_OK && size > 0; ) {
280+
281+ /* hash this address into a TLB entry: */
282+ tlb = (*bus_device->tme_bus_device_tlb_hash)
283+ (bus_device,
284+ address_init,
285+ TME_BUS_CYCLE_READ);
286+
287+ /* busy this TLB entry: */
288+ tme_bus_tlb_busy(tlb);
289+
290+ /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't
291+ allow reading, reload it: */
292+ if (tme_bus_tlb_is_invalid(tlb)
293+ || address_init < tlb->tme_bus_tlb_addr_first
294+ || address_init > tlb->tme_bus_tlb_addr_last
295+ || (tlb->tme_bus_tlb_emulator_off_read == TME_EMULATOR_OFF_UNDEF
296+ && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_READ))) {
297+
298+ /* unbusy this TLB entry for filling: */
299+ tme_bus_tlb_unbusy_fill(tlb);
300+
301+ /* pass this TLB's token: */
302+ tlb_local.tme_bus_tlb_token = tlb->tme_bus_tlb_token;
303+
304+ /* get our bus connection: */
305+ conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *,
306+ bus_device->tme_bus_device_connection,
307+ &bus_device->tme_bus_device_connection_rwlock);
308+
309+ /* unlock the device: */
310+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
311+
312+ /* reload the TLB entry: */
313+ err = (*conn_bus->tme_bus_tlb_fill)
314+ (conn_bus,
315+ &tlb_local,
316+ address_init,
317+ TME_BUS_CYCLE_READ);
318+
319+ /* lock the device: */
320+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
321+
322+ /* return if we couldn't fill the TLB entry: */
323+ if (err != TME_OK) {
324+ return (err);
325+ }
326+
327+ /* store the TLB entry: */
328+ *tlb = tlb_local;
329+
330+ /* loop to check the newly filled TLB entry: */
331+ continue;
332+ }
333+
334+ /* if this TLB entry allows fast reading: */
335+ if (tlb->tme_bus_tlb_emulator_off_read != TME_EMULATOR_OFF_UNDEF) {
336+
337+ /* see how many bytes we can fast read from this TLB entry,
338+ starting at this address: */
339+ count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init);
340+
341+ /* read that many bytes or size bytes, whichever is smaller: */
342+ count_minus_one = TME_MIN(count_minus_one,
343+ (size - 1));
344+ count = count_minus_one + 1;
345+ assert (count != 0);
346+
347+ /* do the bus read: */
348+ tme_memory_bus_read_buffer((tlb->tme_bus_tlb_emulator_off_read + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint16_t));
349+
350+ /* unbusy this TLB entry: */
351+ tme_bus_tlb_unbusy(tlb);
352+ }
353+
354+ /* otherwise, we have to do a slow read: */
355+ else {
356+
357+ /* get the size of this bus cycle: */
358+ count = (1 << TME_BUS16_LOG2);
359+ count -= (address_init & (count - 1));
360+ count = TME_MIN(count, size);
361+
362+ /* fill the cycle structure: */
363+ cycle.tme_bus_cycle_type = TME_BUS_CYCLE_READ;
364+ cycle.tme_bus_cycle_size = count;
365+ cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */
366+ cycle.tme_bus_cycle_buffer_increment = 1;
367+ cycle.tme_bus_cycle_lane_routing
368+ = (bus_device->tme_bus_device_router
369+ + TME_BUS_ROUTER_INIT_INDEX(TME_BUS16_LOG2, count, address_init));
370+
371+ /* XXX this should come from a socket configuration: */
372+ cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS16_LOG2);
373+
374+ /* form the physical address for the bus cycle handler: */
375+ address_resp = tlb->tme_bus_tlb_addr_offset + address_init;
376+ shift = tlb->tme_bus_tlb_addr_shift;
377+ if (shift < 0) {
378+ address_resp <<= (0 - shift);
379+ }
380+ else if (shift > 0) {
381+ address_resp >>= shift;
382+ }
383+ cycle.tme_bus_cycle_address = address_resp;
384+
385+ /* unbusy this TLB entry: */
386+ tme_bus_tlb_unbusy(tlb);
387+
388+ /* unlock the device: */
389+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
390+
391+ /* run the bus cycle: */
392+ err = (*tlb->tme_bus_tlb_cycle)
393+ (tlb->tme_bus_tlb_cycle_private, &cycle);
394+
395+ /* if the TLB entry was invalidated before the read: */
396+ if (err == EBADF
397+ && tme_bus_tlb_is_invalid(tlb)) {
398+ count = 0;
399+ }
400+
401+ /* otherwise, any other error might be a bus error: */
402+ else if (err != TME_OK) {
403+ err = tme_bus_tlb_fault(tlb, &cycle, err);
404+ assert (err != TME_OK);
405+ }
406+
407+ /* lock the device: */
408+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
409+ }
410+
411+ /* update the address, buffer, and size and continue: */
412+ address_init += count;
413+ buffer += count;
414+ size -= count;
415+ }
416+
417+ return (err);
418+}
419+
420+/* the 16-bit bus master DMA write function: */
421+int
422+tme_bus_device_dma_write_16(struct tme_bus_device *bus_device,
423+ tme_bus_addr_t address_init,
424+ tme_bus_addr_t size,
425+ const tme_uint8_t *buffer,
426+ unsigned int locks)
427+{
428+ struct tme_bus_tlb *tlb, tlb_local;
429+ struct tme_bus_connection *conn_bus;
430+ tme_bus_addr_t count_minus_one, count;
431+ struct tme_bus_cycle cycle;
432+ tme_bus_addr_t address_resp;
433+ int shift;
434+ int err;
435+
436+ /* assume no error: */
437+ err = TME_OK;
438+
439+ /* loop while we have more bytes to write: */
440+ for (; err == TME_OK && size > 0; ) {
441+
442+ /* hash this address into a TLB entry: */
443+ tlb = (*bus_device->tme_bus_device_tlb_hash)
444+ (bus_device,
445+ address_init,
446+ TME_BUS_CYCLE_WRITE);
447+
448+ /* busy this TLB entry: */
449+ tme_bus_tlb_busy(tlb);
450+
451+ /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't
452+ allow writing, reload it: */
453+ if (tme_bus_tlb_is_invalid(tlb)
454+ || address_init < tlb->tme_bus_tlb_addr_first
455+ || address_init > tlb->tme_bus_tlb_addr_last
456+ || (tlb->tme_bus_tlb_emulator_off_write == TME_EMULATOR_OFF_UNDEF
457+ && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_WRITE))) {
458+
459+ /* unbusy this TLB entry for filling: */
460+ tme_bus_tlb_unbusy_fill(tlb);
461+
462+ /* pass this TLB's token: */
463+ tlb_local.tme_bus_tlb_token = tlb->tme_bus_tlb_token;
464+
465+ /* get our bus connection: */
466+ conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *,
467+ bus_device->tme_bus_device_connection,
468+ &bus_device->tme_bus_device_connection_rwlock);
469+
470+ /* unlock the device: */
471+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
472+
473+ /* reload the TLB entry: */
474+ err = (*conn_bus->tme_bus_tlb_fill)
475+ (conn_bus,
476+ &tlb_local,
477+ address_init,
478+ TME_BUS_CYCLE_WRITE);
479+
480+ /* lock the device: */
481+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
482+
483+ /* return if we couldn't fill the TLB entry: */
484+ if (err != TME_OK) {
485+ return (err);
486+ }
487+
488+ /* store the TLB entry: */
489+ *tlb = tlb_local;
490+
491+ /* loop to check the newly filled TLB entry: */
492+ continue;
493+ }
494+
495+ /* if this TLB entry allows fast writing: */
496+ if (tlb->tme_bus_tlb_emulator_off_write != TME_EMULATOR_OFF_UNDEF) {
497+
498+ /* see how many bytes we can fast write to this TLB entry,
499+ starting at this address: */
500+ count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init);
501+
502+ /* write that many bytes or size bytes, whichever is smaller: */
503+ count_minus_one = TME_MIN(count_minus_one,
504+ (size - 1));
505+ count = count_minus_one + 1;
506+ assert (count != 0);
507+
508+ /* do the bus write: */
509+ tme_memory_bus_write_buffer((tlb->tme_bus_tlb_emulator_off_write + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint16_t));
510+
511+ /* unbusy this TLB entry: */
512+ tme_bus_tlb_unbusy(tlb);
513+ }
514+
515+ /* otherwise, we have to do a slow write: */
516+ else {
517+
518+ /* get the size of this bus cycle: */
519+ count = (1 << TME_BUS16_LOG2);
520+ count -= (address_init & (count - 1));
521+ count = TME_MIN(count, size);
522+
523+ /* fill the cycle structure: */
524+ cycle.tme_bus_cycle_type = TME_BUS_CYCLE_WRITE;
525+ cycle.tme_bus_cycle_size = count;
526+ cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */
527+ cycle.tme_bus_cycle_buffer_increment = 1;
528+ cycle.tme_bus_cycle_lane_routing
529+ = (bus_device->tme_bus_device_router
530+ + TME_BUS_ROUTER_INIT_INDEX(TME_BUS16_LOG2, count, address_init));
531+
532+ /* XXX this should come from a socket configuration: */
533+ cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS16_LOG2);
534+
535+ /* form the physical address for the bus cycle handler: */
536+ address_resp = tlb->tme_bus_tlb_addr_offset + address_init;
537+ shift = tlb->tme_bus_tlb_addr_shift;
538+ if (shift < 0) {
539+ address_resp <<= (0 - shift);
540+ }
541+ else if (shift > 0) {
542+ address_resp >>= shift;
543+ }
544+ cycle.tme_bus_cycle_address = address_resp;
545+
546+ /* unbusy this TLB entry: */
547+ tme_bus_tlb_unbusy(tlb);
548+
549+ /* unlock the device: */
550+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
551+
552+ /* run the bus cycle: */
553+ err = (*tlb->tme_bus_tlb_cycle)
554+ (tlb->tme_bus_tlb_cycle_private, &cycle);
555+
556+ /* if the TLB entry was invalidated before the write: */
557+ if (err == EBADF
558+ && tme_bus_tlb_is_invalid(tlb)) {
559+ count = 0;
560+ }
561+
562+ /* otherwise, any other error might be a bus error: */
563+ else if (err != TME_OK) {
564+ err = tme_bus_tlb_fault(tlb, &cycle, err);
565+ assert (err != TME_OK);
566+ }
567+
568+ /* lock the device: */
569+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
570+ }
571+
572+ /* update the address, buffer, and size and continue: */
573+ address_init += count;
574+ buffer += count;
575+ size -= count;
576+ }
577+
578+ return (err);
579+}
580+
581+/* the 32-bit big-endian bus master bus router: */
582+const tme_bus_lane_t tme_bus_device_router_32eb[TME_BUS_ROUTER_INIT_SIZE(TME_BUS32_LOG2)] = {
583+
584+ /* initiator maximum cycle size: 8 bits
585+ initiator address offset: 0 bits
586+ responder bus port size: 8 bits
587+ responder port least lane: D7-D0: */
588+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
589+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
590+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
591+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
592+
593+ /* initiator maximum cycle size: 8 bits
594+ initiator address offset: 0 bits
595+ responder bus port size: 8 bits
596+ responder port least lane: D15-D8: */
597+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
598+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
599+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
600+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
601+
602+ /* initiator maximum cycle size: 8 bits
603+ initiator address offset: 0 bits
604+ responder bus port size: 8 bits
605+ responder port least lane: D23-D16: */
606+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
607+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
608+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
609+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
610+
611+ /* initiator maximum cycle size: 8 bits
612+ initiator address offset: 0 bits
613+ responder bus port size: 8 bits
614+ responder port least lane: D31-D24: */
615+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
616+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
617+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
618+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
619+
620+ /* initiator maximum cycle size: 8 bits
621+ initiator address offset: 0 bits
622+ responder bus port size: 16 bits
623+ responder port least lane: D7-D0: */
624+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
625+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
626+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
627+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
628+
629+ /* initiator maximum cycle size: 8 bits
630+ initiator address offset: 0 bits
631+ responder bus port size: 16 bits
632+ responder port least lane: D15-D8: */
633+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
634+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
635+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
636+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
637+
638+ /* initiator maximum cycle size: 8 bits
639+ initiator address offset: 0 bits
640+ responder bus port size: 16 bits
641+ responder port least lane: D23-D16: */
642+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
643+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
644+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
645+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
646+
647+ /* initiator maximum cycle size: 8 bits
648+ initiator address offset: 0 bits
649+ responder bus port size: 16 bits
650+ responder port least lane: D31-D24
651+ (responder port not correctly positioned for this initiator): */
652+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
653+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
654+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
655+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
656+
657+ /* initiator maximum cycle size: 8 bits
658+ initiator address offset: 0 bits
659+ responder bus port size: 32 bits
660+ responder port least lane: D7-D0: */
661+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
662+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
663+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
664+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
665+
666+ /* initiator maximum cycle size: 8 bits
667+ initiator address offset: 0 bits
668+ responder bus port size: 32 bits
669+ responder port least lane: D15-D8
670+ (responder port not correctly positioned for this initiator): */
671+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
672+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
673+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
674+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
675+
676+ /* initiator maximum cycle size: 8 bits
677+ initiator address offset: 0 bits
678+ responder bus port size: 32 bits
679+ responder port least lane: D23-D16
680+ (responder port not correctly positioned for this initiator): */
681+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
682+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
683+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
684+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
685+
686+ /* initiator maximum cycle size: 8 bits
687+ initiator address offset: 0 bits
688+ responder bus port size: 32 bits
689+ responder port least lane: D31-D24
690+ (responder port not correctly positioned for this initiator): */
691+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
692+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
693+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
694+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
695+
696+ /* initiator maximum cycle size: 8 bits
697+ initiator address offset: 8 bits
698+ responder bus port size: 8 bits
699+ responder port least lane: D7-D0: */
700+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
701+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
702+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
703+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
704+
705+ /* initiator maximum cycle size: 8 bits
706+ initiator address offset: 8 bits
707+ responder bus port size: 8 bits
708+ responder port least lane: D15-D8: */
709+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
710+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
711+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
712+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
713+
714+ /* initiator maximum cycle size: 8 bits
715+ initiator address offset: 8 bits
716+ responder bus port size: 8 bits
717+ responder port least lane: D23-D16: */
718+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
719+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
720+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
721+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
722+
723+ /* initiator maximum cycle size: 8 bits
724+ initiator address offset: 8 bits
725+ responder bus port size: 8 bits
726+ responder port least lane: D31-D24: */
727+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
728+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
729+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
730+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
731+
732+ /* initiator maximum cycle size: 8 bits
733+ initiator address offset: 8 bits
734+ responder bus port size: 16 bits
735+ responder port least lane: D7-D0: */
736+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
737+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
738+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
739+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
740+
741+ /* initiator maximum cycle size: 8 bits
742+ initiator address offset: 8 bits
743+ responder bus port size: 16 bits
744+ responder port least lane: D15-D8: */
745+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
746+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
747+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
748+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
749+
750+ /* initiator maximum cycle size: 8 bits
751+ initiator address offset: 8 bits
752+ responder bus port size: 16 bits
753+ responder port least lane: D23-D16: */
754+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
755+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
756+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
757+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
758+
759+ /* initiator maximum cycle size: 8 bits
760+ initiator address offset: 8 bits
761+ responder bus port size: 16 bits
762+ responder port least lane: D31-D24
763+ (responder port not correctly positioned for this initiator): */
764+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
765+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
766+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
767+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
768+
769+ /* initiator maximum cycle size: 8 bits
770+ initiator address offset: 8 bits
771+ responder bus port size: 32 bits
772+ responder port least lane: D7-D0: */
773+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
774+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
775+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
776+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
777+
778+ /* initiator maximum cycle size: 8 bits
779+ initiator address offset: 8 bits
780+ responder bus port size: 32 bits
781+ responder port least lane: D15-D8
782+ (responder port not correctly positioned for this initiator): */
783+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
784+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
785+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
786+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
787+
788+ /* initiator maximum cycle size: 8 bits
789+ initiator address offset: 8 bits
790+ responder bus port size: 32 bits
791+ responder port least lane: D23-D16
792+ (responder port not correctly positioned for this initiator): */
793+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
794+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
795+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
796+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
797+
798+ /* initiator maximum cycle size: 8 bits
799+ initiator address offset: 8 bits
800+ responder bus port size: 32 bits
801+ responder port least lane: D31-D24
802+ (responder port not correctly positioned for this initiator): */
803+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
804+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
805+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
806+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
807+
808+ /* initiator maximum cycle size: 8 bits
809+ initiator address offset: 16 bits
810+ responder bus port size: 8 bits
811+ responder port least lane: D7-D0: */
812+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
813+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
814+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
815+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
816+
817+ /* initiator maximum cycle size: 8 bits
818+ initiator address offset: 16 bits
819+ responder bus port size: 8 bits
820+ responder port least lane: D15-D8: */
821+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
822+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
823+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
824+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
825+
826+ /* initiator maximum cycle size: 8 bits
827+ initiator address offset: 16 bits
828+ responder bus port size: 8 bits
829+ responder port least lane: D23-D16: */
830+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
831+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
832+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
833+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
834+
835+ /* initiator maximum cycle size: 8 bits
836+ initiator address offset: 16 bits
837+ responder bus port size: 8 bits
838+ responder port least lane: D31-D24: */
839+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
840+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
841+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
842+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
843+
844+ /* initiator maximum cycle size: 8 bits
845+ initiator address offset: 16 bits
846+ responder bus port size: 16 bits
847+ responder port least lane: D7-D0: */
848+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
849+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
850+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
851+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
852+
853+ /* initiator maximum cycle size: 8 bits
854+ initiator address offset: 16 bits
855+ responder bus port size: 16 bits
856+ responder port least lane: D15-D8: */
857+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
858+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
859+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
860+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
861+
862+ /* initiator maximum cycle size: 8 bits
863+ initiator address offset: 16 bits
864+ responder bus port size: 16 bits
865+ responder port least lane: D23-D16: */
866+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
867+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
868+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
869+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
870+
871+ /* initiator maximum cycle size: 8 bits
872+ initiator address offset: 16 bits
873+ responder bus port size: 16 bits
874+ responder port least lane: D31-D24
875+ (responder port not correctly positioned for this initiator): */
876+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
877+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
878+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
879+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
880+
881+ /* initiator maximum cycle size: 8 bits
882+ initiator address offset: 16 bits
883+ responder bus port size: 32 bits
884+ responder port least lane: D7-D0: */
885+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
886+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
887+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
888+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
889+
890+ /* initiator maximum cycle size: 8 bits
891+ initiator address offset: 16 bits
892+ responder bus port size: 32 bits
893+ responder port least lane: D15-D8
894+ (responder port not correctly positioned for this initiator): */
895+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
896+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
897+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
898+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
899+
900+ /* initiator maximum cycle size: 8 bits
901+ initiator address offset: 16 bits
902+ responder bus port size: 32 bits
903+ responder port least lane: D23-D16
904+ (responder port not correctly positioned for this initiator): */
905+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
906+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
907+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
908+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
909+
910+ /* initiator maximum cycle size: 8 bits
911+ initiator address offset: 16 bits
912+ responder bus port size: 32 bits
913+ responder port least lane: D31-D24
914+ (responder port not correctly positioned for this initiator): */
915+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
916+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
917+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
918+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
919+
920+ /* initiator maximum cycle size: 8 bits
921+ initiator address offset: 24 bits
922+ responder bus port size: 8 bits
923+ responder port least lane: D7-D0: */
924+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
925+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
926+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
927+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
928+
929+ /* initiator maximum cycle size: 8 bits
930+ initiator address offset: 24 bits
931+ responder bus port size: 8 bits
932+ responder port least lane: D15-D8: */
933+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
934+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
935+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
936+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
937+
938+ /* initiator maximum cycle size: 8 bits
939+ initiator address offset: 24 bits
940+ responder bus port size: 8 bits
941+ responder port least lane: D23-D16: */
942+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
943+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
944+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
945+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
946+
947+ /* initiator maximum cycle size: 8 bits
948+ initiator address offset: 24 bits
949+ responder bus port size: 8 bits
950+ responder port least lane: D31-D24: */
951+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
952+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
953+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
954+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
955+
956+ /* initiator maximum cycle size: 8 bits
957+ initiator address offset: 24 bits
958+ responder bus port size: 16 bits
959+ responder port least lane: D7-D0: */
960+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
961+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
962+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
963+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
964+
965+ /* initiator maximum cycle size: 8 bits
966+ initiator address offset: 24 bits
967+ responder bus port size: 16 bits
968+ responder port least lane: D15-D8: */
969+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
970+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
971+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
972+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
973+
974+ /* initiator maximum cycle size: 8 bits
975+ initiator address offset: 24 bits
976+ responder bus port size: 16 bits
977+ responder port least lane: D23-D16: */
978+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
979+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
980+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
981+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
982+
983+ /* initiator maximum cycle size: 8 bits
984+ initiator address offset: 24 bits
985+ responder bus port size: 16 bits
986+ responder port least lane: D31-D24
987+ (responder port not correctly positioned for this initiator): */
988+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
989+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
990+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
991+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
992+
993+ /* initiator maximum cycle size: 8 bits
994+ initiator address offset: 24 bits
995+ responder bus port size: 32 bits
996+ responder port least lane: D7-D0: */
997+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
998+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
999+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1000+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1001+
1002+ /* initiator maximum cycle size: 8 bits
1003+ initiator address offset: 24 bits
1004+ responder bus port size: 32 bits
1005+ responder port least lane: D15-D8
1006+ (responder port not correctly positioned for this initiator): */
1007+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1008+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1009+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1010+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1011+
1012+ /* initiator maximum cycle size: 8 bits
1013+ initiator address offset: 24 bits
1014+ responder bus port size: 32 bits
1015+ responder port least lane: D23-D16
1016+ (responder port not correctly positioned for this initiator): */
1017+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1018+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1019+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1020+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1021+
1022+ /* initiator maximum cycle size: 8 bits
1023+ initiator address offset: 24 bits
1024+ responder bus port size: 32 bits
1025+ responder port least lane: D31-D24
1026+ (responder port not correctly positioned for this initiator): */
1027+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1028+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1029+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1030+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1031+
1032+ /* initiator maximum cycle size: 16 bits
1033+ initiator address offset: 0 bits
1034+ responder bus port size: 8 bits
1035+ responder port least lane: D7-D0: */
1036+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1037+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1038+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1039+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1040+
1041+ /* initiator maximum cycle size: 16 bits
1042+ initiator address offset: 0 bits
1043+ responder bus port size: 8 bits
1044+ responder port least lane: D15-D8: */
1045+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1046+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1047+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1048+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1049+
1050+ /* initiator maximum cycle size: 16 bits
1051+ initiator address offset: 0 bits
1052+ responder bus port size: 8 bits
1053+ responder port least lane: D23-D16: */
1054+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1055+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1056+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1057+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1058+
1059+ /* initiator maximum cycle size: 16 bits
1060+ initiator address offset: 0 bits
1061+ responder bus port size: 8 bits
1062+ responder port least lane: D31-D24: */
1063+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1064+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1065+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1066+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1067+
1068+ /* initiator maximum cycle size: 16 bits
1069+ initiator address offset: 0 bits
1070+ responder bus port size: 16 bits
1071+ responder port least lane: D7-D0: */
1072+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1073+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1074+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1075+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1076+
1077+ /* initiator maximum cycle size: 16 bits
1078+ initiator address offset: 0 bits
1079+ responder bus port size: 16 bits
1080+ responder port least lane: D15-D8: */
1081+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1082+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1083+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1084+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1085+
1086+ /* initiator maximum cycle size: 16 bits
1087+ initiator address offset: 0 bits
1088+ responder bus port size: 16 bits
1089+ responder port least lane: D23-D16: */
1090+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1091+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1092+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1093+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1094+
1095+ /* initiator maximum cycle size: 16 bits
1096+ initiator address offset: 0 bits
1097+ responder bus port size: 16 bits
1098+ responder port least lane: D31-D24
1099+ (responder port not correctly positioned for this initiator): */
1100+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1101+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1102+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1103+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1104+
1105+ /* initiator maximum cycle size: 16 bits
1106+ initiator address offset: 0 bits
1107+ responder bus port size: 32 bits
1108+ responder port least lane: D7-D0: */
1109+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1110+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1111+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1112+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1113+
1114+ /* initiator maximum cycle size: 16 bits
1115+ initiator address offset: 0 bits
1116+ responder bus port size: 32 bits
1117+ responder port least lane: D15-D8
1118+ (responder port not correctly positioned for this initiator): */
1119+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1120+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1121+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1122+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1123+
1124+ /* initiator maximum cycle size: 16 bits
1125+ initiator address offset: 0 bits
1126+ responder bus port size: 32 bits
1127+ responder port least lane: D23-D16
1128+ (responder port not correctly positioned for this initiator): */
1129+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1130+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1131+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1132+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1133+
1134+ /* initiator maximum cycle size: 16 bits
1135+ initiator address offset: 0 bits
1136+ responder bus port size: 32 bits
1137+ responder port least lane: D31-D24
1138+ (responder port not correctly positioned for this initiator): */
1139+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1140+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
1141+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1142+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1143+
1144+ /* initiator maximum cycle size: 16 bits
1145+ initiator address offset: 8 bits
1146+ responder bus port size: 8 bits
1147+ responder port least lane: D7-D0: */
1148+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1149+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1150+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1151+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1152+
1153+ /* initiator maximum cycle size: 16 bits
1154+ initiator address offset: 8 bits
1155+ responder bus port size: 8 bits
1156+ responder port least lane: D15-D8: */
1157+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1158+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1159+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1160+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1161+
1162+ /* initiator maximum cycle size: 16 bits
1163+ initiator address offset: 8 bits
1164+ responder bus port size: 8 bits
1165+ responder port least lane: D23-D16: */
1166+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1167+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1168+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1169+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1170+
1171+ /* initiator maximum cycle size: 16 bits
1172+ initiator address offset: 8 bits
1173+ responder bus port size: 8 bits
1174+ responder port least lane: D31-D24: */
1175+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1176+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1177+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1178+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1179+
1180+ /* initiator maximum cycle size: 16 bits
1181+ initiator address offset: 8 bits
1182+ responder bus port size: 16 bits
1183+ responder port least lane: D7-D0: */
1184+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1185+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1186+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1187+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1188+
1189+ /* initiator maximum cycle size: 16 bits
1190+ initiator address offset: 8 bits
1191+ responder bus port size: 16 bits
1192+ responder port least lane: D15-D8: */
1193+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1194+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1195+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1196+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1197+
1198+ /* initiator maximum cycle size: 16 bits
1199+ initiator address offset: 8 bits
1200+ responder bus port size: 16 bits
1201+ responder port least lane: D23-D16: */
1202+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1203+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1204+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1205+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1206+
1207+ /* initiator maximum cycle size: 16 bits
1208+ initiator address offset: 8 bits
1209+ responder bus port size: 16 bits
1210+ responder port least lane: D31-D24
1211+ (responder port not correctly positioned for this initiator): */
1212+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1213+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1214+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1215+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1216+
1217+ /* initiator maximum cycle size: 16 bits
1218+ initiator address offset: 8 bits
1219+ responder bus port size: 32 bits
1220+ responder port least lane: D7-D0: */
1221+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1222+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1223+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1224+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1225+
1226+ /* initiator maximum cycle size: 16 bits
1227+ initiator address offset: 8 bits
1228+ responder bus port size: 32 bits
1229+ responder port least lane: D15-D8
1230+ (responder port not correctly positioned for this initiator): */
1231+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1232+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1233+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1234+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1235+
1236+ /* initiator maximum cycle size: 16 bits
1237+ initiator address offset: 8 bits
1238+ responder bus port size: 32 bits
1239+ responder port least lane: D23-D16
1240+ (responder port not correctly positioned for this initiator): */
1241+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1242+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1243+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1244+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1245+
1246+ /* initiator maximum cycle size: 16 bits
1247+ initiator address offset: 8 bits
1248+ responder bus port size: 32 bits
1249+ responder port least lane: D31-D24
1250+ (responder port not correctly positioned for this initiator): */
1251+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1252+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1253+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1254+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1255+
1256+ /* initiator maximum cycle size: 16 bits
1257+ initiator address offset: 16 bits
1258+ responder bus port size: 8 bits
1259+ responder port least lane: D7-D0: */
1260+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1),
1261+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1262+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1263+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1264+
1265+ /* initiator maximum cycle size: 16 bits
1266+ initiator address offset: 16 bits
1267+ responder bus port size: 8 bits
1268+ responder port least lane: D15-D8: */
1269+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1270+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
1271+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1272+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1273+
1274+ /* initiator maximum cycle size: 16 bits
1275+ initiator address offset: 16 bits
1276+ responder bus port size: 8 bits
1277+ responder port least lane: D23-D16: */
1278+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1279+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1280+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1281+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1282+
1283+ /* initiator maximum cycle size: 16 bits
1284+ initiator address offset: 16 bits
1285+ responder bus port size: 8 bits
1286+ responder port least lane: D31-D24: */
1287+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1288+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1289+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1290+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1291+
1292+ /* initiator maximum cycle size: 16 bits
1293+ initiator address offset: 16 bits
1294+ responder bus port size: 16 bits
1295+ responder port least lane: D7-D0: */
1296+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1),
1297+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
1298+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1299+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1300+
1301+ /* initiator maximum cycle size: 16 bits
1302+ initiator address offset: 16 bits
1303+ responder bus port size: 16 bits
1304+ responder port least lane: D15-D8: */
1305+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1306+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
1307+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1308+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1309+
1310+ /* initiator maximum cycle size: 16 bits
1311+ initiator address offset: 16 bits
1312+ responder bus port size: 16 bits
1313+ responder port least lane: D23-D16: */
1314+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1315+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1316+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1317+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1318+
1319+ /* initiator maximum cycle size: 16 bits
1320+ initiator address offset: 16 bits
1321+ responder bus port size: 16 bits
1322+ responder port least lane: D31-D24
1323+ (responder port not correctly positioned for this initiator): */
1324+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1325+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1326+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1327+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1328+
1329+ /* initiator maximum cycle size: 16 bits
1330+ initiator address offset: 16 bits
1331+ responder bus port size: 32 bits
1332+ responder port least lane: D7-D0: */
1333+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1),
1334+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
1335+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1336+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1337+
1338+ /* initiator maximum cycle size: 16 bits
1339+ initiator address offset: 16 bits
1340+ responder bus port size: 32 bits
1341+ responder port least lane: D15-D8
1342+ (responder port not correctly positioned for this initiator): */
1343+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1344+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
1345+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1346+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1347+
1348+ /* initiator maximum cycle size: 16 bits
1349+ initiator address offset: 16 bits
1350+ responder bus port size: 32 bits
1351+ responder port least lane: D23-D16
1352+ (responder port not correctly positioned for this initiator): */
1353+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1354+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1355+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1356+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1357+
1358+ /* initiator maximum cycle size: 16 bits
1359+ initiator address offset: 16 bits
1360+ responder bus port size: 32 bits
1361+ responder port least lane: D31-D24
1362+ (responder port not correctly positioned for this initiator): */
1363+ /* D7-D0 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1364+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1365+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
1366+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1367+
1368+ /* initiator maximum cycle size: 16 bits
1369+ initiator address offset: 24 bits
1370+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1371+ responder bus port size: 8 bits
1372+ responder port least lane: D7-D0: */
1373+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1374+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1375+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1376+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1377+
1378+ /* initiator maximum cycle size: 16 bits
1379+ initiator address offset: 24 bits
1380+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1381+ responder bus port size: 8 bits
1382+ responder port least lane: D15-D8: */
1383+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1384+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1385+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1386+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1387+
1388+ /* initiator maximum cycle size: 16 bits
1389+ initiator address offset: 24 bits
1390+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1391+ responder bus port size: 8 bits
1392+ responder port least lane: D23-D16: */
1393+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1394+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1395+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1396+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1397+
1398+ /* initiator maximum cycle size: 16 bits
1399+ initiator address offset: 24 bits
1400+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1401+ responder bus port size: 8 bits
1402+ responder port least lane: D31-D24: */
1403+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1404+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1405+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1406+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1407+
1408+ /* initiator maximum cycle size: 16 bits
1409+ initiator address offset: 24 bits
1410+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1411+ responder bus port size: 16 bits
1412+ responder port least lane: D7-D0: */
1413+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1414+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1415+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1416+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1417+
1418+ /* initiator maximum cycle size: 16 bits
1419+ initiator address offset: 24 bits
1420+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1421+ responder bus port size: 16 bits
1422+ responder port least lane: D15-D8: */
1423+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1424+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1425+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1426+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1427+
1428+ /* initiator maximum cycle size: 16 bits
1429+ initiator address offset: 24 bits
1430+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1431+ responder bus port size: 16 bits
1432+ responder port least lane: D23-D16: */
1433+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1434+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1435+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1436+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1437+
1438+ /* initiator maximum cycle size: 16 bits
1439+ initiator address offset: 24 bits
1440+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1441+ responder bus port size: 16 bits
1442+ responder port least lane: D31-D24
1443+ (responder port not correctly positioned for this initiator): */
1444+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1445+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1446+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1447+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1448+
1449+ /* initiator maximum cycle size: 16 bits
1450+ initiator address offset: 24 bits
1451+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1452+ responder bus port size: 32 bits
1453+ responder port least lane: D7-D0: */
1454+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1455+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1456+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1457+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1458+
1459+ /* initiator maximum cycle size: 16 bits
1460+ initiator address offset: 24 bits
1461+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1462+ responder bus port size: 32 bits
1463+ responder port least lane: D15-D8
1464+ (responder port not correctly positioned for this initiator): */
1465+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1466+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1467+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1468+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1469+
1470+ /* initiator maximum cycle size: 16 bits
1471+ initiator address offset: 24 bits
1472+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1473+ responder bus port size: 32 bits
1474+ responder port least lane: D23-D16
1475+ (responder port not correctly positioned for this initiator): */
1476+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1477+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1478+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1479+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1480+
1481+ /* initiator maximum cycle size: 16 bits
1482+ initiator address offset: 24 bits
1483+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
1484+ responder bus port size: 32 bits
1485+ responder port least lane: D31-D24
1486+ (responder port not correctly positioned for this initiator): */
1487+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1488+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1489+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1490+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1491+
1492+ /* initiator maximum cycle size: 24 bits
1493+ initiator address offset: 0 bits
1494+ responder bus port size: 8 bits
1495+ responder port least lane: D7-D0: */
1496+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1497+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1498+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1499+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1500+
1501+ /* initiator maximum cycle size: 24 bits
1502+ initiator address offset: 0 bits
1503+ responder bus port size: 8 bits
1504+ responder port least lane: D15-D8: */
1505+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1506+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
1507+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1508+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1509+
1510+ /* initiator maximum cycle size: 24 bits
1511+ initiator address offset: 0 bits
1512+ responder bus port size: 8 bits
1513+ responder port least lane: D23-D16: */
1514+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1515+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1516+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1517+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1518+
1519+ /* initiator maximum cycle size: 24 bits
1520+ initiator address offset: 0 bits
1521+ responder bus port size: 8 bits
1522+ responder port least lane: D31-D24: */
1523+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1524+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1525+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1526+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1527+
1528+ /* initiator maximum cycle size: 24 bits
1529+ initiator address offset: 0 bits
1530+ responder bus port size: 16 bits
1531+ responder port least lane: D7-D0: */
1532+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1533+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
1534+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1535+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1536+
1537+ /* initiator maximum cycle size: 24 bits
1538+ initiator address offset: 0 bits
1539+ responder bus port size: 16 bits
1540+ responder port least lane: D15-D8: */
1541+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1542+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
1543+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1544+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1545+
1546+ /* initiator maximum cycle size: 24 bits
1547+ initiator address offset: 0 bits
1548+ responder bus port size: 16 bits
1549+ responder port least lane: D23-D16: */
1550+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1551+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1552+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1553+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1554+
1555+ /* initiator maximum cycle size: 24 bits
1556+ initiator address offset: 0 bits
1557+ responder bus port size: 16 bits
1558+ responder port least lane: D31-D24
1559+ (responder port not correctly positioned for this initiator): */
1560+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1561+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1562+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1563+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1564+
1565+ /* initiator maximum cycle size: 24 bits
1566+ initiator address offset: 0 bits
1567+ responder bus port size: 32 bits
1568+ responder port least lane: D7-D0: */
1569+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1570+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
1571+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1572+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1573+
1574+ /* initiator maximum cycle size: 24 bits
1575+ initiator address offset: 0 bits
1576+ responder bus port size: 32 bits
1577+ responder port least lane: D15-D8
1578+ (responder port not correctly positioned for this initiator): */
1579+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1580+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
1581+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1582+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1583+
1584+ /* initiator maximum cycle size: 24 bits
1585+ initiator address offset: 0 bits
1586+ responder bus port size: 32 bits
1587+ responder port least lane: D23-D16
1588+ (responder port not correctly positioned for this initiator): */
1589+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1590+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1591+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1592+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1593+
1594+ /* initiator maximum cycle size: 24 bits
1595+ initiator address offset: 0 bits
1596+ responder bus port size: 32 bits
1597+ responder port least lane: D31-D24
1598+ (responder port not correctly positioned for this initiator): */
1599+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
1600+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1601+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1602+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1603+
1604+ /* initiator maximum cycle size: 24 bits
1605+ initiator address offset: 8 bits
1606+ responder bus port size: 8 bits
1607+ responder port least lane: D7-D0: */
1608+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2),
1609+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1610+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1611+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1612+
1613+ /* initiator maximum cycle size: 24 bits
1614+ initiator address offset: 8 bits
1615+ responder bus port size: 8 bits
1616+ responder port least lane: D15-D8: */
1617+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1618+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1619+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1620+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1621+
1622+ /* initiator maximum cycle size: 24 bits
1623+ initiator address offset: 8 bits
1624+ responder bus port size: 8 bits
1625+ responder port least lane: D23-D16: */
1626+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1627+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1628+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1629+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1630+
1631+ /* initiator maximum cycle size: 24 bits
1632+ initiator address offset: 8 bits
1633+ responder bus port size: 8 bits
1634+ responder port least lane: D31-D24: */
1635+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1636+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1637+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1638+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1639+
1640+ /* initiator maximum cycle size: 24 bits
1641+ initiator address offset: 8 bits
1642+ responder bus port size: 16 bits
1643+ responder port least lane: D7-D0: */
1644+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2),
1645+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1646+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1647+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1648+
1649+ /* initiator maximum cycle size: 24 bits
1650+ initiator address offset: 8 bits
1651+ responder bus port size: 16 bits
1652+ responder port least lane: D15-D8: */
1653+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1654+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1655+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1656+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1657+
1658+ /* initiator maximum cycle size: 24 bits
1659+ initiator address offset: 8 bits
1660+ responder bus port size: 16 bits
1661+ responder port least lane: D23-D16: */
1662+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1663+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1664+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1665+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1666+
1667+ /* initiator maximum cycle size: 24 bits
1668+ initiator address offset: 8 bits
1669+ responder bus port size: 16 bits
1670+ responder port least lane: D31-D24
1671+ (responder port not correctly positioned for this initiator): */
1672+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1673+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1674+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1675+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1676+
1677+ /* initiator maximum cycle size: 24 bits
1678+ initiator address offset: 8 bits
1679+ responder bus port size: 32 bits
1680+ responder port least lane: D7-D0: */
1681+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2),
1682+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1683+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1684+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1685+
1686+ /* initiator maximum cycle size: 24 bits
1687+ initiator address offset: 8 bits
1688+ responder bus port size: 32 bits
1689+ responder port least lane: D15-D8
1690+ (responder port not correctly positioned for this initiator): */
1691+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1692+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
1693+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1694+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1695+
1696+ /* initiator maximum cycle size: 24 bits
1697+ initiator address offset: 8 bits
1698+ responder bus port size: 32 bits
1699+ responder port least lane: D23-D16
1700+ (responder port not correctly positioned for this initiator): */
1701+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1702+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1703+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
1704+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1705+
1706+ /* initiator maximum cycle size: 24 bits
1707+ initiator address offset: 8 bits
1708+ responder bus port size: 32 bits
1709+ responder port least lane: D31-D24
1710+ (responder port not correctly positioned for this initiator): */
1711+ /* D7-D0 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1712+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1713+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1714+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
1715+
1716+ /* initiator maximum cycle size: 24 bits
1717+ initiator address offset: 16 bits
1718+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1719+ responder bus port size: 8 bits
1720+ responder port least lane: D7-D0: */
1721+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1722+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1723+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1724+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1725+
1726+ /* initiator maximum cycle size: 24 bits
1727+ initiator address offset: 16 bits
1728+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1729+ responder bus port size: 8 bits
1730+ responder port least lane: D15-D8: */
1731+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1732+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1733+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1734+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1735+
1736+ /* initiator maximum cycle size: 24 bits
1737+ initiator address offset: 16 bits
1738+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1739+ responder bus port size: 8 bits
1740+ responder port least lane: D23-D16: */
1741+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1742+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1743+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1744+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1745+
1746+ /* initiator maximum cycle size: 24 bits
1747+ initiator address offset: 16 bits
1748+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1749+ responder bus port size: 8 bits
1750+ responder port least lane: D31-D24: */
1751+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1752+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1753+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1754+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1755+
1756+ /* initiator maximum cycle size: 24 bits
1757+ initiator address offset: 16 bits
1758+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1759+ responder bus port size: 16 bits
1760+ responder port least lane: D7-D0: */
1761+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1762+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1763+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1764+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1765+
1766+ /* initiator maximum cycle size: 24 bits
1767+ initiator address offset: 16 bits
1768+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1769+ responder bus port size: 16 bits
1770+ responder port least lane: D15-D8: */
1771+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1772+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1773+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1774+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1775+
1776+ /* initiator maximum cycle size: 24 bits
1777+ initiator address offset: 16 bits
1778+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1779+ responder bus port size: 16 bits
1780+ responder port least lane: D23-D16: */
1781+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1782+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1783+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1784+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1785+
1786+ /* initiator maximum cycle size: 24 bits
1787+ initiator address offset: 16 bits
1788+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1789+ responder bus port size: 16 bits
1790+ responder port least lane: D31-D24
1791+ (responder port not correctly positioned for this initiator): */
1792+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1793+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1794+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1795+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1796+
1797+ /* initiator maximum cycle size: 24 bits
1798+ initiator address offset: 16 bits
1799+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1800+ responder bus port size: 32 bits
1801+ responder port least lane: D7-D0: */
1802+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1803+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1804+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1805+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1806+
1807+ /* initiator maximum cycle size: 24 bits
1808+ initiator address offset: 16 bits
1809+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1810+ responder bus port size: 32 bits
1811+ responder port least lane: D15-D8
1812+ (responder port not correctly positioned for this initiator): */
1813+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1814+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1815+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1816+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1817+
1818+ /* initiator maximum cycle size: 24 bits
1819+ initiator address offset: 16 bits
1820+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1821+ responder bus port size: 32 bits
1822+ responder port least lane: D23-D16
1823+ (responder port not correctly positioned for this initiator): */
1824+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1825+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1826+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1827+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1828+
1829+ /* initiator maximum cycle size: 24 bits
1830+ initiator address offset: 16 bits
1831+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
1832+ responder bus port size: 32 bits
1833+ responder port least lane: D31-D24
1834+ (responder port not correctly positioned for this initiator): */
1835+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1836+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1837+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1838+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1839+
1840+ /* initiator maximum cycle size: 24 bits
1841+ initiator address offset: 24 bits
1842+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1843+ responder bus port size: 8 bits
1844+ responder port least lane: D7-D0: */
1845+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1846+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1847+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1848+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1849+
1850+ /* initiator maximum cycle size: 24 bits
1851+ initiator address offset: 24 bits
1852+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1853+ responder bus port size: 8 bits
1854+ responder port least lane: D15-D8: */
1855+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1856+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1857+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1858+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1859+
1860+ /* initiator maximum cycle size: 24 bits
1861+ initiator address offset: 24 bits
1862+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1863+ responder bus port size: 8 bits
1864+ responder port least lane: D23-D16: */
1865+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1866+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1867+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1868+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1869+
1870+ /* initiator maximum cycle size: 24 bits
1871+ initiator address offset: 24 bits
1872+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1873+ responder bus port size: 8 bits
1874+ responder port least lane: D31-D24: */
1875+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1876+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1877+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1878+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1879+
1880+ /* initiator maximum cycle size: 24 bits
1881+ initiator address offset: 24 bits
1882+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1883+ responder bus port size: 16 bits
1884+ responder port least lane: D7-D0: */
1885+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1886+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1887+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1888+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1889+
1890+ /* initiator maximum cycle size: 24 bits
1891+ initiator address offset: 24 bits
1892+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1893+ responder bus port size: 16 bits
1894+ responder port least lane: D15-D8: */
1895+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1896+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1897+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1898+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1899+
1900+ /* initiator maximum cycle size: 24 bits
1901+ initiator address offset: 24 bits
1902+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1903+ responder bus port size: 16 bits
1904+ responder port least lane: D23-D16: */
1905+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1906+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1907+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1908+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1909+
1910+ /* initiator maximum cycle size: 24 bits
1911+ initiator address offset: 24 bits
1912+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1913+ responder bus port size: 16 bits
1914+ responder port least lane: D31-D24
1915+ (responder port not correctly positioned for this initiator): */
1916+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1917+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1918+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1919+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1920+
1921+ /* initiator maximum cycle size: 24 bits
1922+ initiator address offset: 24 bits
1923+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1924+ responder bus port size: 32 bits
1925+ responder port least lane: D7-D0: */
1926+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1927+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1928+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1929+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1930+
1931+ /* initiator maximum cycle size: 24 bits
1932+ initiator address offset: 24 bits
1933+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1934+ responder bus port size: 32 bits
1935+ responder port least lane: D15-D8
1936+ (responder port not correctly positioned for this initiator): */
1937+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1938+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1939+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1940+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1941+
1942+ /* initiator maximum cycle size: 24 bits
1943+ initiator address offset: 24 bits
1944+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1945+ responder bus port size: 32 bits
1946+ responder port least lane: D23-D16
1947+ (responder port not correctly positioned for this initiator): */
1948+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1949+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1950+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1951+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1952+
1953+ /* initiator maximum cycle size: 24 bits
1954+ initiator address offset: 24 bits
1955+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
1956+ responder bus port size: 32 bits
1957+ responder port least lane: D31-D24
1958+ (responder port not correctly positioned for this initiator): */
1959+ /* D7-D0 */ TME_BUS_LANE_ABORT,
1960+ /* D15-D8 */ TME_BUS_LANE_ABORT,
1961+ /* D23-D16 */ TME_BUS_LANE_ABORT,
1962+ /* D31-D24 */ TME_BUS_LANE_ABORT,
1963+
1964+ /* initiator maximum cycle size: 32 bits
1965+ initiator address offset: 0 bits
1966+ responder bus port size: 8 bits
1967+ responder port least lane: D7-D0: */
1968+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3),
1969+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1970+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1971+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1972+
1973+ /* initiator maximum cycle size: 32 bits
1974+ initiator address offset: 0 bits
1975+ responder bus port size: 8 bits
1976+ responder port least lane: D15-D8: */
1977+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
1978+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
1979+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1980+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1981+
1982+ /* initiator maximum cycle size: 32 bits
1983+ initiator address offset: 0 bits
1984+ responder bus port size: 8 bits
1985+ responder port least lane: D23-D16: */
1986+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
1987+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1988+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
1989+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
1990+
1991+ /* initiator maximum cycle size: 32 bits
1992+ initiator address offset: 0 bits
1993+ responder bus port size: 8 bits
1994+ responder port least lane: D31-D24: */
1995+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
1996+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
1997+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
1998+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
1999+
2000+ /* initiator maximum cycle size: 32 bits
2001+ initiator address offset: 0 bits
2002+ responder bus port size: 16 bits
2003+ responder port least lane: D7-D0: */
2004+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3),
2005+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
2006+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2007+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2008+
2009+ /* initiator maximum cycle size: 32 bits
2010+ initiator address offset: 0 bits
2011+ responder bus port size: 16 bits
2012+ responder port least lane: D15-D8: */
2013+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
2014+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
2015+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
2016+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2017+
2018+ /* initiator maximum cycle size: 32 bits
2019+ initiator address offset: 0 bits
2020+ responder bus port size: 16 bits
2021+ responder port least lane: D23-D16: */
2022+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
2023+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
2024+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
2025+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2026+
2027+ /* initiator maximum cycle size: 32 bits
2028+ initiator address offset: 0 bits
2029+ responder bus port size: 16 bits
2030+ responder port least lane: D31-D24
2031+ (responder port not correctly positioned for this initiator): */
2032+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
2033+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
2034+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2035+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2036+
2037+ /* initiator maximum cycle size: 32 bits
2038+ initiator address offset: 0 bits
2039+ responder bus port size: 32 bits
2040+ responder port least lane: D7-D0: */
2041+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3),
2042+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
2043+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
2044+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2045+
2046+ /* initiator maximum cycle size: 32 bits
2047+ initiator address offset: 0 bits
2048+ responder bus port size: 32 bits
2049+ responder port least lane: D15-D8
2050+ (responder port not correctly positioned for this initiator): */
2051+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
2052+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2),
2053+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
2054+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2055+
2056+ /* initiator maximum cycle size: 32 bits
2057+ initiator address offset: 0 bits
2058+ responder bus port size: 32 bits
2059+ responder port least lane: D23-D16
2060+ (responder port not correctly positioned for this initiator): */
2061+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
2062+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
2063+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
2064+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2065+
2066+ /* initiator maximum cycle size: 32 bits
2067+ initiator address offset: 0 bits
2068+ responder bus port size: 32 bits
2069+ responder port least lane: D31-D24
2070+ (responder port not correctly positioned for this initiator): */
2071+ /* D7-D0 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
2072+ /* D15-D8 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
2073+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2074+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2075+
2076+ /* initiator maximum cycle size: 32 bits
2077+ initiator address offset: 8 bits
2078+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2079+ responder bus port size: 8 bits
2080+ responder port least lane: D7-D0: */
2081+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2082+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2083+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2084+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2085+
2086+ /* initiator maximum cycle size: 32 bits
2087+ initiator address offset: 8 bits
2088+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2089+ responder bus port size: 8 bits
2090+ responder port least lane: D15-D8: */
2091+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2092+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2093+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2094+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2095+
2096+ /* initiator maximum cycle size: 32 bits
2097+ initiator address offset: 8 bits
2098+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2099+ responder bus port size: 8 bits
2100+ responder port least lane: D23-D16: */
2101+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2102+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2103+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2104+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2105+
2106+ /* initiator maximum cycle size: 32 bits
2107+ initiator address offset: 8 bits
2108+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2109+ responder bus port size: 8 bits
2110+ responder port least lane: D31-D24: */
2111+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2112+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2113+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2114+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2115+
2116+ /* initiator maximum cycle size: 32 bits
2117+ initiator address offset: 8 bits
2118+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2119+ responder bus port size: 16 bits
2120+ responder port least lane: D7-D0: */
2121+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2122+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2123+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2124+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2125+
2126+ /* initiator maximum cycle size: 32 bits
2127+ initiator address offset: 8 bits
2128+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2129+ responder bus port size: 16 bits
2130+ responder port least lane: D15-D8: */
2131+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2132+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2133+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2134+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2135+
2136+ /* initiator maximum cycle size: 32 bits
2137+ initiator address offset: 8 bits
2138+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2139+ responder bus port size: 16 bits
2140+ responder port least lane: D23-D16: */
2141+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2142+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2143+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2144+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2145+
2146+ /* initiator maximum cycle size: 32 bits
2147+ initiator address offset: 8 bits
2148+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2149+ responder bus port size: 16 bits
2150+ responder port least lane: D31-D24
2151+ (responder port not correctly positioned for this initiator): */
2152+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2153+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2154+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2155+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2156+
2157+ /* initiator maximum cycle size: 32 bits
2158+ initiator address offset: 8 bits
2159+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2160+ responder bus port size: 32 bits
2161+ responder port least lane: D7-D0: */
2162+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2163+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2164+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2165+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2166+
2167+ /* initiator maximum cycle size: 32 bits
2168+ initiator address offset: 8 bits
2169+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2170+ responder bus port size: 32 bits
2171+ responder port least lane: D15-D8
2172+ (responder port not correctly positioned for this initiator): */
2173+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2174+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2175+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2176+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2177+
2178+ /* initiator maximum cycle size: 32 bits
2179+ initiator address offset: 8 bits
2180+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2181+ responder bus port size: 32 bits
2182+ responder port least lane: D23-D16
2183+ (responder port not correctly positioned for this initiator): */
2184+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2185+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2186+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2187+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2188+
2189+ /* initiator maximum cycle size: 32 bits
2190+ initiator address offset: 8 bits
2191+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
2192+ responder bus port size: 32 bits
2193+ responder port least lane: D31-D24
2194+ (responder port not correctly positioned for this initiator): */
2195+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2196+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2197+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2198+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2199+
2200+ /* initiator maximum cycle size: 32 bits
2201+ initiator address offset: 16 bits
2202+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2203+ responder bus port size: 8 bits
2204+ responder port least lane: D7-D0: */
2205+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2206+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2207+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2208+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2209+
2210+ /* initiator maximum cycle size: 32 bits
2211+ initiator address offset: 16 bits
2212+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2213+ responder bus port size: 8 bits
2214+ responder port least lane: D15-D8: */
2215+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2216+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2217+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2218+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2219+
2220+ /* initiator maximum cycle size: 32 bits
2221+ initiator address offset: 16 bits
2222+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2223+ responder bus port size: 8 bits
2224+ responder port least lane: D23-D16: */
2225+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2226+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2227+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2228+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2229+
2230+ /* initiator maximum cycle size: 32 bits
2231+ initiator address offset: 16 bits
2232+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2233+ responder bus port size: 8 bits
2234+ responder port least lane: D31-D24: */
2235+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2236+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2237+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2238+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2239+
2240+ /* initiator maximum cycle size: 32 bits
2241+ initiator address offset: 16 bits
2242+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2243+ responder bus port size: 16 bits
2244+ responder port least lane: D7-D0: */
2245+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2246+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2247+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2248+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2249+
2250+ /* initiator maximum cycle size: 32 bits
2251+ initiator address offset: 16 bits
2252+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2253+ responder bus port size: 16 bits
2254+ responder port least lane: D15-D8: */
2255+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2256+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2257+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2258+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2259+
2260+ /* initiator maximum cycle size: 32 bits
2261+ initiator address offset: 16 bits
2262+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2263+ responder bus port size: 16 bits
2264+ responder port least lane: D23-D16: */
2265+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2266+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2267+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2268+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2269+
2270+ /* initiator maximum cycle size: 32 bits
2271+ initiator address offset: 16 bits
2272+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2273+ responder bus port size: 16 bits
2274+ responder port least lane: D31-D24
2275+ (responder port not correctly positioned for this initiator): */
2276+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2277+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2278+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2279+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2280+
2281+ /* initiator maximum cycle size: 32 bits
2282+ initiator address offset: 16 bits
2283+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2284+ responder bus port size: 32 bits
2285+ responder port least lane: D7-D0: */
2286+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2287+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2288+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2289+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2290+
2291+ /* initiator maximum cycle size: 32 bits
2292+ initiator address offset: 16 bits
2293+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2294+ responder bus port size: 32 bits
2295+ responder port least lane: D15-D8
2296+ (responder port not correctly positioned for this initiator): */
2297+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2298+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2299+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2300+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2301+
2302+ /* initiator maximum cycle size: 32 bits
2303+ initiator address offset: 16 bits
2304+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2305+ responder bus port size: 32 bits
2306+ responder port least lane: D23-D16
2307+ (responder port not correctly positioned for this initiator): */
2308+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2309+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2310+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2311+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2312+
2313+ /* initiator maximum cycle size: 32 bits
2314+ initiator address offset: 16 bits
2315+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
2316+ responder bus port size: 32 bits
2317+ responder port least lane: D31-D24
2318+ (responder port not correctly positioned for this initiator): */
2319+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2320+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2321+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2322+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2323+
2324+ /* initiator maximum cycle size: 32 bits
2325+ initiator address offset: 24 bits
2326+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2327+ responder bus port size: 8 bits
2328+ responder port least lane: D7-D0: */
2329+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2330+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2331+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2332+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2333+
2334+ /* initiator maximum cycle size: 32 bits
2335+ initiator address offset: 24 bits
2336+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2337+ responder bus port size: 8 bits
2338+ responder port least lane: D15-D8: */
2339+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2340+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2341+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2342+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2343+
2344+ /* initiator maximum cycle size: 32 bits
2345+ initiator address offset: 24 bits
2346+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2347+ responder bus port size: 8 bits
2348+ responder port least lane: D23-D16: */
2349+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2350+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2351+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2352+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2353+
2354+ /* initiator maximum cycle size: 32 bits
2355+ initiator address offset: 24 bits
2356+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2357+ responder bus port size: 8 bits
2358+ responder port least lane: D31-D24: */
2359+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2360+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2361+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2362+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2363+
2364+ /* initiator maximum cycle size: 32 bits
2365+ initiator address offset: 24 bits
2366+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2367+ responder bus port size: 16 bits
2368+ responder port least lane: D7-D0: */
2369+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2370+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2371+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2372+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2373+
2374+ /* initiator maximum cycle size: 32 bits
2375+ initiator address offset: 24 bits
2376+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2377+ responder bus port size: 16 bits
2378+ responder port least lane: D15-D8: */
2379+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2380+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2381+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2382+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2383+
2384+ /* initiator maximum cycle size: 32 bits
2385+ initiator address offset: 24 bits
2386+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2387+ responder bus port size: 16 bits
2388+ responder port least lane: D23-D16: */
2389+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2390+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2391+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2392+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2393+
2394+ /* initiator maximum cycle size: 32 bits
2395+ initiator address offset: 24 bits
2396+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2397+ responder bus port size: 16 bits
2398+ responder port least lane: D31-D24
2399+ (responder port not correctly positioned for this initiator): */
2400+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2401+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2402+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2403+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2404+
2405+ /* initiator maximum cycle size: 32 bits
2406+ initiator address offset: 24 bits
2407+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2408+ responder bus port size: 32 bits
2409+ responder port least lane: D7-D0: */
2410+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2411+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2412+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2413+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2414+
2415+ /* initiator maximum cycle size: 32 bits
2416+ initiator address offset: 24 bits
2417+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2418+ responder bus port size: 32 bits
2419+ responder port least lane: D15-D8
2420+ (responder port not correctly positioned for this initiator): */
2421+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2422+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2423+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2424+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2425+
2426+ /* initiator maximum cycle size: 32 bits
2427+ initiator address offset: 24 bits
2428+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2429+ responder bus port size: 32 bits
2430+ responder port least lane: D23-D16
2431+ (responder port not correctly positioned for this initiator): */
2432+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2433+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2434+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2435+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2436+
2437+ /* initiator maximum cycle size: 32 bits
2438+ initiator address offset: 24 bits
2439+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
2440+ responder bus port size: 32 bits
2441+ responder port least lane: D31-D24
2442+ (responder port not correctly positioned for this initiator): */
2443+ /* D7-D0 */ TME_BUS_LANE_ABORT,
2444+ /* D15-D8 */ TME_BUS_LANE_ABORT,
2445+ /* D23-D16 */ TME_BUS_LANE_ABORT,
2446+ /* D31-D24 */ TME_BUS_LANE_ABORT,
2447+};
2448+
2449+/* the 32-bit little-endian bus master bus router: */
2450+const tme_bus_lane_t tme_bus_device_router_32el[TME_BUS_ROUTER_INIT_SIZE(TME_BUS32_LOG2)] = {
2451+
2452+ /* initiator maximum cycle size: 8 bits
2453+ initiator address offset: 0 bits
2454+ responder bus port size: 8 bits
2455+ responder port least lane: D7-D0: */
2456+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
2457+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2458+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2459+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2460+
2461+ /* initiator maximum cycle size: 8 bits
2462+ initiator address offset: 0 bits
2463+ responder bus port size: 8 bits
2464+ responder port least lane: D15-D8: */
2465+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2466+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2467+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2468+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2469+
2470+ /* initiator maximum cycle size: 8 bits
2471+ initiator address offset: 0 bits
2472+ responder bus port size: 8 bits
2473+ responder port least lane: D23-D16: */
2474+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2475+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2476+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2477+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2478+
2479+ /* initiator maximum cycle size: 8 bits
2480+ initiator address offset: 0 bits
2481+ responder bus port size: 8 bits
2482+ responder port least lane: D31-D24: */
2483+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2484+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2485+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2486+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2487+
2488+ /* initiator maximum cycle size: 8 bits
2489+ initiator address offset: 0 bits
2490+ responder bus port size: 16 bits
2491+ responder port least lane: D7-D0: */
2492+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
2493+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2494+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2495+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2496+
2497+ /* initiator maximum cycle size: 8 bits
2498+ initiator address offset: 0 bits
2499+ responder bus port size: 16 bits
2500+ responder port least lane: D15-D8: */
2501+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2502+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2503+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2504+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2505+
2506+ /* initiator maximum cycle size: 8 bits
2507+ initiator address offset: 0 bits
2508+ responder bus port size: 16 bits
2509+ responder port least lane: D23-D16: */
2510+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2511+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2512+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2513+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2514+
2515+ /* initiator maximum cycle size: 8 bits
2516+ initiator address offset: 0 bits
2517+ responder bus port size: 16 bits
2518+ responder port least lane: D31-D24
2519+ (responder port not correctly positioned for this initiator): */
2520+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2521+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2522+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2523+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2524+
2525+ /* initiator maximum cycle size: 8 bits
2526+ initiator address offset: 0 bits
2527+ responder bus port size: 32 bits
2528+ responder port least lane: D7-D0: */
2529+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
2530+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2531+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2532+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2533+
2534+ /* initiator maximum cycle size: 8 bits
2535+ initiator address offset: 0 bits
2536+ responder bus port size: 32 bits
2537+ responder port least lane: D15-D8
2538+ (responder port not correctly positioned for this initiator): */
2539+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2540+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2541+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2542+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2543+
2544+ /* initiator maximum cycle size: 8 bits
2545+ initiator address offset: 0 bits
2546+ responder bus port size: 32 bits
2547+ responder port least lane: D23-D16
2548+ (responder port not correctly positioned for this initiator): */
2549+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2550+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2551+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2552+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2553+
2554+ /* initiator maximum cycle size: 8 bits
2555+ initiator address offset: 0 bits
2556+ responder bus port size: 32 bits
2557+ responder port least lane: D31-D24
2558+ (responder port not correctly positioned for this initiator): */
2559+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2560+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2561+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2562+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2563+
2564+ /* initiator maximum cycle size: 8 bits
2565+ initiator address offset: 8 bits
2566+ responder bus port size: 8 bits
2567+ responder port least lane: D7-D0: */
2568+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2569+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2570+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2571+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2572+
2573+ /* initiator maximum cycle size: 8 bits
2574+ initiator address offset: 8 bits
2575+ responder bus port size: 8 bits
2576+ responder port least lane: D15-D8: */
2577+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2578+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
2579+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2580+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2581+
2582+ /* initiator maximum cycle size: 8 bits
2583+ initiator address offset: 8 bits
2584+ responder bus port size: 8 bits
2585+ responder port least lane: D23-D16: */
2586+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2587+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2588+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2589+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2590+
2591+ /* initiator maximum cycle size: 8 bits
2592+ initiator address offset: 8 bits
2593+ responder bus port size: 8 bits
2594+ responder port least lane: D31-D24: */
2595+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2596+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2597+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2598+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2599+
2600+ /* initiator maximum cycle size: 8 bits
2601+ initiator address offset: 8 bits
2602+ responder bus port size: 16 bits
2603+ responder port least lane: D7-D0: */
2604+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2605+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
2606+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2607+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2608+
2609+ /* initiator maximum cycle size: 8 bits
2610+ initiator address offset: 8 bits
2611+ responder bus port size: 16 bits
2612+ responder port least lane: D15-D8: */
2613+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2614+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
2615+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2616+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2617+
2618+ /* initiator maximum cycle size: 8 bits
2619+ initiator address offset: 8 bits
2620+ responder bus port size: 16 bits
2621+ responder port least lane: D23-D16: */
2622+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2623+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2624+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2625+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2626+
2627+ /* initiator maximum cycle size: 8 bits
2628+ initiator address offset: 8 bits
2629+ responder bus port size: 16 bits
2630+ responder port least lane: D31-D24
2631+ (responder port not correctly positioned for this initiator): */
2632+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2633+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2634+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2635+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2636+
2637+ /* initiator maximum cycle size: 8 bits
2638+ initiator address offset: 8 bits
2639+ responder bus port size: 32 bits
2640+ responder port least lane: D7-D0: */
2641+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2642+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
2643+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2644+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2645+
2646+ /* initiator maximum cycle size: 8 bits
2647+ initiator address offset: 8 bits
2648+ responder bus port size: 32 bits
2649+ responder port least lane: D15-D8
2650+ (responder port not correctly positioned for this initiator): */
2651+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2652+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
2653+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2654+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2655+
2656+ /* initiator maximum cycle size: 8 bits
2657+ initiator address offset: 8 bits
2658+ responder bus port size: 32 bits
2659+ responder port least lane: D23-D16
2660+ (responder port not correctly positioned for this initiator): */
2661+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2662+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2663+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2664+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2665+
2666+ /* initiator maximum cycle size: 8 bits
2667+ initiator address offset: 8 bits
2668+ responder bus port size: 32 bits
2669+ responder port least lane: D31-D24
2670+ (responder port not correctly positioned for this initiator): */
2671+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2672+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2673+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2674+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2675+
2676+ /* initiator maximum cycle size: 8 bits
2677+ initiator address offset: 16 bits
2678+ responder bus port size: 8 bits
2679+ responder port least lane: D7-D0: */
2680+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2681+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2682+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2683+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2684+
2685+ /* initiator maximum cycle size: 8 bits
2686+ initiator address offset: 16 bits
2687+ responder bus port size: 8 bits
2688+ responder port least lane: D15-D8: */
2689+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2690+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2691+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2692+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2693+
2694+ /* initiator maximum cycle size: 8 bits
2695+ initiator address offset: 16 bits
2696+ responder bus port size: 8 bits
2697+ responder port least lane: D23-D16: */
2698+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2699+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2700+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
2701+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2702+
2703+ /* initiator maximum cycle size: 8 bits
2704+ initiator address offset: 16 bits
2705+ responder bus port size: 8 bits
2706+ responder port least lane: D31-D24: */
2707+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2708+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2709+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2710+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2711+
2712+ /* initiator maximum cycle size: 8 bits
2713+ initiator address offset: 16 bits
2714+ responder bus port size: 16 bits
2715+ responder port least lane: D7-D0: */
2716+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2717+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2718+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2719+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2720+
2721+ /* initiator maximum cycle size: 8 bits
2722+ initiator address offset: 16 bits
2723+ responder bus port size: 16 bits
2724+ responder port least lane: D15-D8: */
2725+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2726+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2727+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
2728+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2729+
2730+ /* initiator maximum cycle size: 8 bits
2731+ initiator address offset: 16 bits
2732+ responder bus port size: 16 bits
2733+ responder port least lane: D23-D16: */
2734+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2735+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2736+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
2737+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2738+
2739+ /* initiator maximum cycle size: 8 bits
2740+ initiator address offset: 16 bits
2741+ responder bus port size: 16 bits
2742+ responder port least lane: D31-D24
2743+ (responder port not correctly positioned for this initiator): */
2744+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2745+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2746+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2747+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2748+
2749+ /* initiator maximum cycle size: 8 bits
2750+ initiator address offset: 16 bits
2751+ responder bus port size: 32 bits
2752+ responder port least lane: D7-D0: */
2753+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2754+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2755+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
2756+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2757+
2758+ /* initiator maximum cycle size: 8 bits
2759+ initiator address offset: 16 bits
2760+ responder bus port size: 32 bits
2761+ responder port least lane: D15-D8
2762+ (responder port not correctly positioned for this initiator): */
2763+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2764+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2765+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
2766+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2767+
2768+ /* initiator maximum cycle size: 8 bits
2769+ initiator address offset: 16 bits
2770+ responder bus port size: 32 bits
2771+ responder port least lane: D23-D16
2772+ (responder port not correctly positioned for this initiator): */
2773+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2774+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2775+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
2776+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2777+
2778+ /* initiator maximum cycle size: 8 bits
2779+ initiator address offset: 16 bits
2780+ responder bus port size: 32 bits
2781+ responder port least lane: D31-D24
2782+ (responder port not correctly positioned for this initiator): */
2783+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2784+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2785+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2786+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2787+
2788+ /* initiator maximum cycle size: 8 bits
2789+ initiator address offset: 24 bits
2790+ responder bus port size: 8 bits
2791+ responder port least lane: D7-D0: */
2792+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2793+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2794+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2795+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2796+
2797+ /* initiator maximum cycle size: 8 bits
2798+ initiator address offset: 24 bits
2799+ responder bus port size: 8 bits
2800+ responder port least lane: D15-D8: */
2801+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2802+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2803+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2804+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2805+
2806+ /* initiator maximum cycle size: 8 bits
2807+ initiator address offset: 24 bits
2808+ responder bus port size: 8 bits
2809+ responder port least lane: D23-D16: */
2810+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2811+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2812+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2813+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2814+
2815+ /* initiator maximum cycle size: 8 bits
2816+ initiator address offset: 24 bits
2817+ responder bus port size: 8 bits
2818+ responder port least lane: D31-D24: */
2819+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2820+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2821+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2822+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2823+
2824+ /* initiator maximum cycle size: 8 bits
2825+ initiator address offset: 24 bits
2826+ responder bus port size: 16 bits
2827+ responder port least lane: D7-D0: */
2828+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2829+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2830+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2831+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2832+
2833+ /* initiator maximum cycle size: 8 bits
2834+ initiator address offset: 24 bits
2835+ responder bus port size: 16 bits
2836+ responder port least lane: D15-D8: */
2837+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2838+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2839+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2840+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2841+
2842+ /* initiator maximum cycle size: 8 bits
2843+ initiator address offset: 24 bits
2844+ responder bus port size: 16 bits
2845+ responder port least lane: D23-D16: */
2846+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2847+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2848+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2849+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2850+
2851+ /* initiator maximum cycle size: 8 bits
2852+ initiator address offset: 24 bits
2853+ responder bus port size: 16 bits
2854+ responder port least lane: D31-D24
2855+ (responder port not correctly positioned for this initiator): */
2856+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2857+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2858+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2859+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2860+
2861+ /* initiator maximum cycle size: 8 bits
2862+ initiator address offset: 24 bits
2863+ responder bus port size: 32 bits
2864+ responder port least lane: D7-D0: */
2865+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2866+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2867+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2868+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2869+
2870+ /* initiator maximum cycle size: 8 bits
2871+ initiator address offset: 24 bits
2872+ responder bus port size: 32 bits
2873+ responder port least lane: D15-D8
2874+ (responder port not correctly positioned for this initiator): */
2875+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2876+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2877+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2878+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2879+
2880+ /* initiator maximum cycle size: 8 bits
2881+ initiator address offset: 24 bits
2882+ responder bus port size: 32 bits
2883+ responder port least lane: D23-D16
2884+ (responder port not correctly positioned for this initiator): */
2885+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2886+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2887+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2888+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2889+
2890+ /* initiator maximum cycle size: 8 bits
2891+ initiator address offset: 24 bits
2892+ responder bus port size: 32 bits
2893+ responder port least lane: D31-D24
2894+ (responder port not correctly positioned for this initiator): */
2895+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
2896+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
2897+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2898+ /* D31-D24 */ TME_BUS_LANE_ROUTE(0),
2899+
2900+ /* initiator maximum cycle size: 16 bits
2901+ initiator address offset: 0 bits
2902+ responder bus port size: 8 bits
2903+ responder port least lane: D7-D0: */
2904+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
2905+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2906+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2907+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2908+
2909+ /* initiator maximum cycle size: 16 bits
2910+ initiator address offset: 0 bits
2911+ responder bus port size: 8 bits
2912+ responder port least lane: D15-D8: */
2913+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2914+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
2915+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2916+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2917+
2918+ /* initiator maximum cycle size: 16 bits
2919+ initiator address offset: 0 bits
2920+ responder bus port size: 8 bits
2921+ responder port least lane: D23-D16: */
2922+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2923+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2924+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2925+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2926+
2927+ /* initiator maximum cycle size: 16 bits
2928+ initiator address offset: 0 bits
2929+ responder bus port size: 8 bits
2930+ responder port least lane: D31-D24: */
2931+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2932+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2933+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2934+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2935+
2936+ /* initiator maximum cycle size: 16 bits
2937+ initiator address offset: 0 bits
2938+ responder bus port size: 16 bits
2939+ responder port least lane: D7-D0: */
2940+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
2941+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
2942+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2943+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2944+
2945+ /* initiator maximum cycle size: 16 bits
2946+ initiator address offset: 0 bits
2947+ responder bus port size: 16 bits
2948+ responder port least lane: D15-D8: */
2949+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2950+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
2951+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2952+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2953+
2954+ /* initiator maximum cycle size: 16 bits
2955+ initiator address offset: 0 bits
2956+ responder bus port size: 16 bits
2957+ responder port least lane: D23-D16: */
2958+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2959+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2960+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2961+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2962+
2963+ /* initiator maximum cycle size: 16 bits
2964+ initiator address offset: 0 bits
2965+ responder bus port size: 16 bits
2966+ responder port least lane: D31-D24
2967+ (responder port not correctly positioned for this initiator): */
2968+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2969+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2970+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2971+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2972+
2973+ /* initiator maximum cycle size: 16 bits
2974+ initiator address offset: 0 bits
2975+ responder bus port size: 32 bits
2976+ responder port least lane: D7-D0: */
2977+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
2978+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
2979+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2980+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2981+
2982+ /* initiator maximum cycle size: 16 bits
2983+ initiator address offset: 0 bits
2984+ responder bus port size: 32 bits
2985+ responder port least lane: D15-D8
2986+ (responder port not correctly positioned for this initiator): */
2987+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2988+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
2989+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
2990+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
2991+
2992+ /* initiator maximum cycle size: 16 bits
2993+ initiator address offset: 0 bits
2994+ responder bus port size: 32 bits
2995+ responder port least lane: D23-D16
2996+ (responder port not correctly positioned for this initiator): */
2997+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
2998+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
2999+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
3000+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3001+
3002+ /* initiator maximum cycle size: 16 bits
3003+ initiator address offset: 0 bits
3004+ responder bus port size: 32 bits
3005+ responder port least lane: D31-D24
3006+ (responder port not correctly positioned for this initiator): */
3007+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3008+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3009+ /* D23-D16 */ TME_BUS_LANE_UNDEF,
3010+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3011+
3012+ /* initiator maximum cycle size: 16 bits
3013+ initiator address offset: 8 bits
3014+ responder bus port size: 8 bits
3015+ responder port least lane: D7-D0: */
3016+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3017+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3018+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3019+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3020+
3021+ /* initiator maximum cycle size: 16 bits
3022+ initiator address offset: 8 bits
3023+ responder bus port size: 8 bits
3024+ responder port least lane: D15-D8: */
3025+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3026+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3027+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3028+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3029+
3030+ /* initiator maximum cycle size: 16 bits
3031+ initiator address offset: 8 bits
3032+ responder bus port size: 8 bits
3033+ responder port least lane: D23-D16: */
3034+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3035+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3036+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3037+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3038+
3039+ /* initiator maximum cycle size: 16 bits
3040+ initiator address offset: 8 bits
3041+ responder bus port size: 8 bits
3042+ responder port least lane: D31-D24: */
3043+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3044+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3045+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3046+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3047+
3048+ /* initiator maximum cycle size: 16 bits
3049+ initiator address offset: 8 bits
3050+ responder bus port size: 16 bits
3051+ responder port least lane: D7-D0: */
3052+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3053+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3054+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3055+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3056+
3057+ /* initiator maximum cycle size: 16 bits
3058+ initiator address offset: 8 bits
3059+ responder bus port size: 16 bits
3060+ responder port least lane: D15-D8: */
3061+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3062+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3063+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3064+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3065+
3066+ /* initiator maximum cycle size: 16 bits
3067+ initiator address offset: 8 bits
3068+ responder bus port size: 16 bits
3069+ responder port least lane: D23-D16: */
3070+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3071+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3072+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3073+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3074+
3075+ /* initiator maximum cycle size: 16 bits
3076+ initiator address offset: 8 bits
3077+ responder bus port size: 16 bits
3078+ responder port least lane: D31-D24
3079+ (responder port not correctly positioned for this initiator): */
3080+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3081+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3082+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3083+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3084+
3085+ /* initiator maximum cycle size: 16 bits
3086+ initiator address offset: 8 bits
3087+ responder bus port size: 32 bits
3088+ responder port least lane: D7-D0: */
3089+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3090+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3091+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3092+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3093+
3094+ /* initiator maximum cycle size: 16 bits
3095+ initiator address offset: 8 bits
3096+ responder bus port size: 32 bits
3097+ responder port least lane: D15-D8
3098+ (responder port not correctly positioned for this initiator): */
3099+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3100+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3101+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3102+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3103+
3104+ /* initiator maximum cycle size: 16 bits
3105+ initiator address offset: 8 bits
3106+ responder bus port size: 32 bits
3107+ responder port least lane: D23-D16
3108+ (responder port not correctly positioned for this initiator): */
3109+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3110+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3111+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3112+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3113+
3114+ /* initiator maximum cycle size: 16 bits
3115+ initiator address offset: 8 bits
3116+ responder bus port size: 32 bits
3117+ responder port least lane: D31-D24
3118+ (responder port not correctly positioned for this initiator): */
3119+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3120+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3121+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3122+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3123+
3124+ /* initiator maximum cycle size: 16 bits
3125+ initiator address offset: 16 bits
3126+ responder bus port size: 8 bits
3127+ responder port least lane: D7-D0: */
3128+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3129+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3130+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3131+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3132+
3133+ /* initiator maximum cycle size: 16 bits
3134+ initiator address offset: 16 bits
3135+ responder bus port size: 8 bits
3136+ responder port least lane: D15-D8: */
3137+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3138+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3139+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3140+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3141+
3142+ /* initiator maximum cycle size: 16 bits
3143+ initiator address offset: 16 bits
3144+ responder bus port size: 8 bits
3145+ responder port least lane: D23-D16: */
3146+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3147+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3148+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
3149+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3150+
3151+ /* initiator maximum cycle size: 16 bits
3152+ initiator address offset: 16 bits
3153+ responder bus port size: 8 bits
3154+ responder port least lane: D31-D24: */
3155+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3156+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3157+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3158+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3159+
3160+ /* initiator maximum cycle size: 16 bits
3161+ initiator address offset: 16 bits
3162+ responder bus port size: 16 bits
3163+ responder port least lane: D7-D0: */
3164+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3165+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3166+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3167+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3168+
3169+ /* initiator maximum cycle size: 16 bits
3170+ initiator address offset: 16 bits
3171+ responder bus port size: 16 bits
3172+ responder port least lane: D15-D8: */
3173+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3174+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3175+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
3176+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3177+
3178+ /* initiator maximum cycle size: 16 bits
3179+ initiator address offset: 16 bits
3180+ responder bus port size: 16 bits
3181+ responder port least lane: D23-D16: */
3182+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3183+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3184+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
3185+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3186+
3187+ /* initiator maximum cycle size: 16 bits
3188+ initiator address offset: 16 bits
3189+ responder bus port size: 16 bits
3190+ responder port least lane: D31-D24
3191+ (responder port not correctly positioned for this initiator): */
3192+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3193+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3194+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3195+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3196+
3197+ /* initiator maximum cycle size: 16 bits
3198+ initiator address offset: 16 bits
3199+ responder bus port size: 32 bits
3200+ responder port least lane: D7-D0: */
3201+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3202+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3203+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
3204+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3205+
3206+ /* initiator maximum cycle size: 16 bits
3207+ initiator address offset: 16 bits
3208+ responder bus port size: 32 bits
3209+ responder port least lane: D15-D8
3210+ (responder port not correctly positioned for this initiator): */
3211+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3212+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3213+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
3214+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3215+
3216+ /* initiator maximum cycle size: 16 bits
3217+ initiator address offset: 16 bits
3218+ responder bus port size: 32 bits
3219+ responder port least lane: D23-D16
3220+ (responder port not correctly positioned for this initiator): */
3221+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3222+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3223+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0),
3224+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3225+
3226+ /* initiator maximum cycle size: 16 bits
3227+ initiator address offset: 16 bits
3228+ responder bus port size: 32 bits
3229+ responder port least lane: D31-D24
3230+ (responder port not correctly positioned for this initiator): */
3231+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3232+ /* D15-D8 */ TME_BUS_LANE_UNDEF,
3233+ /* D23-D16 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3234+ /* D31-D24 */ TME_BUS_LANE_ROUTE(1),
3235+
3236+ /* initiator maximum cycle size: 16 bits
3237+ initiator address offset: 24 bits
3238+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3239+ responder bus port size: 8 bits
3240+ responder port least lane: D7-D0: */
3241+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3242+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3243+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3244+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3245+
3246+ /* initiator maximum cycle size: 16 bits
3247+ initiator address offset: 24 bits
3248+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3249+ responder bus port size: 8 bits
3250+ responder port least lane: D15-D8: */
3251+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3252+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3253+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3254+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3255+
3256+ /* initiator maximum cycle size: 16 bits
3257+ initiator address offset: 24 bits
3258+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3259+ responder bus port size: 8 bits
3260+ responder port least lane: D23-D16: */
3261+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3262+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3263+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3264+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3265+
3266+ /* initiator maximum cycle size: 16 bits
3267+ initiator address offset: 24 bits
3268+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3269+ responder bus port size: 8 bits
3270+ responder port least lane: D31-D24: */
3271+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3272+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3273+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3274+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3275+
3276+ /* initiator maximum cycle size: 16 bits
3277+ initiator address offset: 24 bits
3278+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3279+ responder bus port size: 16 bits
3280+ responder port least lane: D7-D0: */
3281+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3282+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3283+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3284+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3285+
3286+ /* initiator maximum cycle size: 16 bits
3287+ initiator address offset: 24 bits
3288+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3289+ responder bus port size: 16 bits
3290+ responder port least lane: D15-D8: */
3291+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3292+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3293+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3294+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3295+
3296+ /* initiator maximum cycle size: 16 bits
3297+ initiator address offset: 24 bits
3298+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3299+ responder bus port size: 16 bits
3300+ responder port least lane: D23-D16: */
3301+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3302+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3303+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3304+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3305+
3306+ /* initiator maximum cycle size: 16 bits
3307+ initiator address offset: 24 bits
3308+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3309+ responder bus port size: 16 bits
3310+ responder port least lane: D31-D24
3311+ (responder port not correctly positioned for this initiator): */
3312+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3313+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3314+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3315+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3316+
3317+ /* initiator maximum cycle size: 16 bits
3318+ initiator address offset: 24 bits
3319+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3320+ responder bus port size: 32 bits
3321+ responder port least lane: D7-D0: */
3322+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3323+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3324+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3325+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3326+
3327+ /* initiator maximum cycle size: 16 bits
3328+ initiator address offset: 24 bits
3329+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3330+ responder bus port size: 32 bits
3331+ responder port least lane: D15-D8
3332+ (responder port not correctly positioned for this initiator): */
3333+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3334+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3335+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3336+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3337+
3338+ /* initiator maximum cycle size: 16 bits
3339+ initiator address offset: 24 bits
3340+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3341+ responder bus port size: 32 bits
3342+ responder port least lane: D23-D16
3343+ (responder port not correctly positioned for this initiator): */
3344+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3345+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3346+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3347+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3348+
3349+ /* initiator maximum cycle size: 16 bits
3350+ initiator address offset: 24 bits
3351+ (a 32-bit initiator cannot request 16 bits at an 24-bit offset - this is an array placeholder)
3352+ responder bus port size: 32 bits
3353+ responder port least lane: D31-D24
3354+ (responder port not correctly positioned for this initiator): */
3355+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3356+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3357+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3358+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3359+
3360+ /* initiator maximum cycle size: 24 bits
3361+ initiator address offset: 0 bits
3362+ responder bus port size: 8 bits
3363+ responder port least lane: D7-D0: */
3364+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
3365+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3366+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3367+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3368+
3369+ /* initiator maximum cycle size: 24 bits
3370+ initiator address offset: 0 bits
3371+ responder bus port size: 8 bits
3372+ responder port least lane: D15-D8: */
3373+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3374+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3375+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3376+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3377+
3378+ /* initiator maximum cycle size: 24 bits
3379+ initiator address offset: 0 bits
3380+ responder bus port size: 8 bits
3381+ responder port least lane: D23-D16: */
3382+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3383+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3384+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3385+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3386+
3387+ /* initiator maximum cycle size: 24 bits
3388+ initiator address offset: 0 bits
3389+ responder bus port size: 8 bits
3390+ responder port least lane: D31-D24: */
3391+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3392+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3393+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3394+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3395+
3396+ /* initiator maximum cycle size: 24 bits
3397+ initiator address offset: 0 bits
3398+ responder bus port size: 16 bits
3399+ responder port least lane: D7-D0: */
3400+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
3401+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3402+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3403+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3404+
3405+ /* initiator maximum cycle size: 24 bits
3406+ initiator address offset: 0 bits
3407+ responder bus port size: 16 bits
3408+ responder port least lane: D15-D8: */
3409+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3410+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3411+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3412+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3413+
3414+ /* initiator maximum cycle size: 24 bits
3415+ initiator address offset: 0 bits
3416+ responder bus port size: 16 bits
3417+ responder port least lane: D23-D16: */
3418+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3419+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3420+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3421+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3422+
3423+ /* initiator maximum cycle size: 24 bits
3424+ initiator address offset: 0 bits
3425+ responder bus port size: 16 bits
3426+ responder port least lane: D31-D24
3427+ (responder port not correctly positioned for this initiator): */
3428+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3429+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3430+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3431+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3432+
3433+ /* initiator maximum cycle size: 24 bits
3434+ initiator address offset: 0 bits
3435+ responder bus port size: 32 bits
3436+ responder port least lane: D7-D0: */
3437+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
3438+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3439+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3440+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3441+
3442+ /* initiator maximum cycle size: 24 bits
3443+ initiator address offset: 0 bits
3444+ responder bus port size: 32 bits
3445+ responder port least lane: D15-D8
3446+ (responder port not correctly positioned for this initiator): */
3447+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3448+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3449+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3450+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3451+
3452+ /* initiator maximum cycle size: 24 bits
3453+ initiator address offset: 0 bits
3454+ responder bus port size: 32 bits
3455+ responder port least lane: D23-D16
3456+ (responder port not correctly positioned for this initiator): */
3457+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3458+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3459+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3460+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3461+
3462+ /* initiator maximum cycle size: 24 bits
3463+ initiator address offset: 0 bits
3464+ responder bus port size: 32 bits
3465+ responder port least lane: D31-D24
3466+ (responder port not correctly positioned for this initiator): */
3467+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3468+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3469+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3470+ /* D31-D24 */ TME_BUS_LANE_UNDEF,
3471+
3472+ /* initiator maximum cycle size: 24 bits
3473+ initiator address offset: 8 bits
3474+ responder bus port size: 8 bits
3475+ responder port least lane: D7-D0: */
3476+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3477+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3478+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3479+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3480+
3481+ /* initiator maximum cycle size: 24 bits
3482+ initiator address offset: 8 bits
3483+ responder bus port size: 8 bits
3484+ responder port least lane: D15-D8: */
3485+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3486+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3487+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3488+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3489+
3490+ /* initiator maximum cycle size: 24 bits
3491+ initiator address offset: 8 bits
3492+ responder bus port size: 8 bits
3493+ responder port least lane: D23-D16: */
3494+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3495+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3496+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3497+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3498+
3499+ /* initiator maximum cycle size: 24 bits
3500+ initiator address offset: 8 bits
3501+ responder bus port size: 8 bits
3502+ responder port least lane: D31-D24: */
3503+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3504+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3505+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3506+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3507+
3508+ /* initiator maximum cycle size: 24 bits
3509+ initiator address offset: 8 bits
3510+ responder bus port size: 16 bits
3511+ responder port least lane: D7-D0: */
3512+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3513+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3514+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3515+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3516+
3517+ /* initiator maximum cycle size: 24 bits
3518+ initiator address offset: 8 bits
3519+ responder bus port size: 16 bits
3520+ responder port least lane: D15-D8: */
3521+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3522+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3523+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3524+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3525+
3526+ /* initiator maximum cycle size: 24 bits
3527+ initiator address offset: 8 bits
3528+ responder bus port size: 16 bits
3529+ responder port least lane: D23-D16: */
3530+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3531+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3532+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3533+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3534+
3535+ /* initiator maximum cycle size: 24 bits
3536+ initiator address offset: 8 bits
3537+ responder bus port size: 16 bits
3538+ responder port least lane: D31-D24
3539+ (responder port not correctly positioned for this initiator): */
3540+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3541+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3542+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3543+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3544+
3545+ /* initiator maximum cycle size: 24 bits
3546+ initiator address offset: 8 bits
3547+ responder bus port size: 32 bits
3548+ responder port least lane: D7-D0: */
3549+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3550+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3551+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3552+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3553+
3554+ /* initiator maximum cycle size: 24 bits
3555+ initiator address offset: 8 bits
3556+ responder bus port size: 32 bits
3557+ responder port least lane: D15-D8
3558+ (responder port not correctly positioned for this initiator): */
3559+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3560+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0),
3561+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3562+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3563+
3564+ /* initiator maximum cycle size: 24 bits
3565+ initiator address offset: 8 bits
3566+ responder bus port size: 32 bits
3567+ responder port least lane: D23-D16
3568+ (responder port not correctly positioned for this initiator): */
3569+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3570+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3571+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1),
3572+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3573+
3574+ /* initiator maximum cycle size: 24 bits
3575+ initiator address offset: 8 bits
3576+ responder bus port size: 32 bits
3577+ responder port least lane: D31-D24
3578+ (responder port not correctly positioned for this initiator): */
3579+ /* D7-D0 */ TME_BUS_LANE_UNDEF,
3580+ /* D15-D8 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3581+ /* D23-D16 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3582+ /* D31-D24 */ TME_BUS_LANE_ROUTE(2),
3583+
3584+ /* initiator maximum cycle size: 24 bits
3585+ initiator address offset: 16 bits
3586+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3587+ responder bus port size: 8 bits
3588+ responder port least lane: D7-D0: */
3589+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3590+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3591+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3592+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3593+
3594+ /* initiator maximum cycle size: 24 bits
3595+ initiator address offset: 16 bits
3596+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3597+ responder bus port size: 8 bits
3598+ responder port least lane: D15-D8: */
3599+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3600+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3601+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3602+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3603+
3604+ /* initiator maximum cycle size: 24 bits
3605+ initiator address offset: 16 bits
3606+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3607+ responder bus port size: 8 bits
3608+ responder port least lane: D23-D16: */
3609+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3610+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3611+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3612+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3613+
3614+ /* initiator maximum cycle size: 24 bits
3615+ initiator address offset: 16 bits
3616+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3617+ responder bus port size: 8 bits
3618+ responder port least lane: D31-D24: */
3619+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3620+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3621+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3622+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3623+
3624+ /* initiator maximum cycle size: 24 bits
3625+ initiator address offset: 16 bits
3626+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3627+ responder bus port size: 16 bits
3628+ responder port least lane: D7-D0: */
3629+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3630+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3631+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3632+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3633+
3634+ /* initiator maximum cycle size: 24 bits
3635+ initiator address offset: 16 bits
3636+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3637+ responder bus port size: 16 bits
3638+ responder port least lane: D15-D8: */
3639+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3640+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3641+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3642+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3643+
3644+ /* initiator maximum cycle size: 24 bits
3645+ initiator address offset: 16 bits
3646+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3647+ responder bus port size: 16 bits
3648+ responder port least lane: D23-D16: */
3649+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3650+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3651+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3652+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3653+
3654+ /* initiator maximum cycle size: 24 bits
3655+ initiator address offset: 16 bits
3656+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3657+ responder bus port size: 16 bits
3658+ responder port least lane: D31-D24
3659+ (responder port not correctly positioned for this initiator): */
3660+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3661+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3662+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3663+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3664+
3665+ /* initiator maximum cycle size: 24 bits
3666+ initiator address offset: 16 bits
3667+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3668+ responder bus port size: 32 bits
3669+ responder port least lane: D7-D0: */
3670+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3671+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3672+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3673+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3674+
3675+ /* initiator maximum cycle size: 24 bits
3676+ initiator address offset: 16 bits
3677+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3678+ responder bus port size: 32 bits
3679+ responder port least lane: D15-D8
3680+ (responder port not correctly positioned for this initiator): */
3681+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3682+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3683+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3684+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3685+
3686+ /* initiator maximum cycle size: 24 bits
3687+ initiator address offset: 16 bits
3688+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3689+ responder bus port size: 32 bits
3690+ responder port least lane: D23-D16
3691+ (responder port not correctly positioned for this initiator): */
3692+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3693+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3694+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3695+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3696+
3697+ /* initiator maximum cycle size: 24 bits
3698+ initiator address offset: 16 bits
3699+ (a 32-bit initiator cannot request 24 bits at an 16-bit offset - this is an array placeholder)
3700+ responder bus port size: 32 bits
3701+ responder port least lane: D31-D24
3702+ (responder port not correctly positioned for this initiator): */
3703+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3704+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3705+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3706+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3707+
3708+ /* initiator maximum cycle size: 24 bits
3709+ initiator address offset: 24 bits
3710+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3711+ responder bus port size: 8 bits
3712+ responder port least lane: D7-D0: */
3713+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3714+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3715+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3716+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3717+
3718+ /* initiator maximum cycle size: 24 bits
3719+ initiator address offset: 24 bits
3720+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3721+ responder bus port size: 8 bits
3722+ responder port least lane: D15-D8: */
3723+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3724+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3725+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3726+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3727+
3728+ /* initiator maximum cycle size: 24 bits
3729+ initiator address offset: 24 bits
3730+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3731+ responder bus port size: 8 bits
3732+ responder port least lane: D23-D16: */
3733+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3734+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3735+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3736+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3737+
3738+ /* initiator maximum cycle size: 24 bits
3739+ initiator address offset: 24 bits
3740+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3741+ responder bus port size: 8 bits
3742+ responder port least lane: D31-D24: */
3743+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3744+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3745+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3746+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3747+
3748+ /* initiator maximum cycle size: 24 bits
3749+ initiator address offset: 24 bits
3750+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3751+ responder bus port size: 16 bits
3752+ responder port least lane: D7-D0: */
3753+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3754+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3755+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3756+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3757+
3758+ /* initiator maximum cycle size: 24 bits
3759+ initiator address offset: 24 bits
3760+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3761+ responder bus port size: 16 bits
3762+ responder port least lane: D15-D8: */
3763+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3764+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3765+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3766+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3767+
3768+ /* initiator maximum cycle size: 24 bits
3769+ initiator address offset: 24 bits
3770+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3771+ responder bus port size: 16 bits
3772+ responder port least lane: D23-D16: */
3773+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3774+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3775+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3776+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3777+
3778+ /* initiator maximum cycle size: 24 bits
3779+ initiator address offset: 24 bits
3780+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3781+ responder bus port size: 16 bits
3782+ responder port least lane: D31-D24
3783+ (responder port not correctly positioned for this initiator): */
3784+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3785+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3786+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3787+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3788+
3789+ /* initiator maximum cycle size: 24 bits
3790+ initiator address offset: 24 bits
3791+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3792+ responder bus port size: 32 bits
3793+ responder port least lane: D7-D0: */
3794+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3795+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3796+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3797+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3798+
3799+ /* initiator maximum cycle size: 24 bits
3800+ initiator address offset: 24 bits
3801+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3802+ responder bus port size: 32 bits
3803+ responder port least lane: D15-D8
3804+ (responder port not correctly positioned for this initiator): */
3805+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3806+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3807+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3808+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3809+
3810+ /* initiator maximum cycle size: 24 bits
3811+ initiator address offset: 24 bits
3812+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3813+ responder bus port size: 32 bits
3814+ responder port least lane: D23-D16
3815+ (responder port not correctly positioned for this initiator): */
3816+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3817+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3818+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3819+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3820+
3821+ /* initiator maximum cycle size: 24 bits
3822+ initiator address offset: 24 bits
3823+ (a 32-bit initiator cannot request 24 bits at an 24-bit offset - this is an array placeholder)
3824+ responder bus port size: 32 bits
3825+ responder port least lane: D31-D24
3826+ (responder port not correctly positioned for this initiator): */
3827+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3828+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3829+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3830+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3831+
3832+ /* initiator maximum cycle size: 32 bits
3833+ initiator address offset: 0 bits
3834+ responder bus port size: 8 bits
3835+ responder port least lane: D7-D0: */
3836+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
3837+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3838+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3839+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
3840+
3841+ /* initiator maximum cycle size: 32 bits
3842+ initiator address offset: 0 bits
3843+ responder bus port size: 8 bits
3844+ responder port least lane: D15-D8: */
3845+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3846+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3847+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3848+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
3849+
3850+ /* initiator maximum cycle size: 32 bits
3851+ initiator address offset: 0 bits
3852+ responder bus port size: 8 bits
3853+ responder port least lane: D23-D16: */
3854+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3855+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3856+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3857+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
3858+
3859+ /* initiator maximum cycle size: 32 bits
3860+ initiator address offset: 0 bits
3861+ responder bus port size: 8 bits
3862+ responder port least lane: D31-D24: */
3863+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3864+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3865+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3866+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3867+
3868+ /* initiator maximum cycle size: 32 bits
3869+ initiator address offset: 0 bits
3870+ responder bus port size: 16 bits
3871+ responder port least lane: D7-D0: */
3872+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
3873+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3874+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3875+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
3876+
3877+ /* initiator maximum cycle size: 32 bits
3878+ initiator address offset: 0 bits
3879+ responder bus port size: 16 bits
3880+ responder port least lane: D15-D8: */
3881+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3882+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3883+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3884+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3) | TME_BUS_LANE_WARN,
3885+
3886+ /* initiator maximum cycle size: 32 bits
3887+ initiator address offset: 0 bits
3888+ responder bus port size: 16 bits
3889+ responder port least lane: D23-D16: */
3890+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3891+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3892+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3893+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3894+
3895+ /* initiator maximum cycle size: 32 bits
3896+ initiator address offset: 0 bits
3897+ responder bus port size: 16 bits
3898+ responder port least lane: D31-D24
3899+ (responder port not correctly positioned for this initiator): */
3900+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3901+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3902+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3903+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3904+
3905+ /* initiator maximum cycle size: 32 bits
3906+ initiator address offset: 0 bits
3907+ responder bus port size: 32 bits
3908+ responder port least lane: D7-D0: */
3909+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0),
3910+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3911+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3912+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3913+
3914+ /* initiator maximum cycle size: 32 bits
3915+ initiator address offset: 0 bits
3916+ responder bus port size: 32 bits
3917+ responder port least lane: D15-D8
3918+ (responder port not correctly positioned for this initiator): */
3919+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3920+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1),
3921+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3922+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3923+
3924+ /* initiator maximum cycle size: 32 bits
3925+ initiator address offset: 0 bits
3926+ responder bus port size: 32 bits
3927+ responder port least lane: D23-D16
3928+ (responder port not correctly positioned for this initiator): */
3929+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3930+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3931+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2),
3932+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3933+
3934+ /* initiator maximum cycle size: 32 bits
3935+ initiator address offset: 0 bits
3936+ responder bus port size: 32 bits
3937+ responder port least lane: D31-D24
3938+ (responder port not correctly positioned for this initiator): */
3939+ /* D7-D0 */ TME_BUS_LANE_ROUTE(0) | TME_BUS_LANE_WARN,
3940+ /* D15-D8 */ TME_BUS_LANE_ROUTE(1) | TME_BUS_LANE_WARN,
3941+ /* D23-D16 */ TME_BUS_LANE_ROUTE(2) | TME_BUS_LANE_WARN,
3942+ /* D31-D24 */ TME_BUS_LANE_ROUTE(3),
3943+
3944+ /* initiator maximum cycle size: 32 bits
3945+ initiator address offset: 8 bits
3946+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
3947+ responder bus port size: 8 bits
3948+ responder port least lane: D7-D0: */
3949+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3950+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3951+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3952+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3953+
3954+ /* initiator maximum cycle size: 32 bits
3955+ initiator address offset: 8 bits
3956+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
3957+ responder bus port size: 8 bits
3958+ responder port least lane: D15-D8: */
3959+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3960+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3961+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3962+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3963+
3964+ /* initiator maximum cycle size: 32 bits
3965+ initiator address offset: 8 bits
3966+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
3967+ responder bus port size: 8 bits
3968+ responder port least lane: D23-D16: */
3969+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3970+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3971+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3972+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3973+
3974+ /* initiator maximum cycle size: 32 bits
3975+ initiator address offset: 8 bits
3976+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
3977+ responder bus port size: 8 bits
3978+ responder port least lane: D31-D24: */
3979+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3980+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3981+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3982+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3983+
3984+ /* initiator maximum cycle size: 32 bits
3985+ initiator address offset: 8 bits
3986+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
3987+ responder bus port size: 16 bits
3988+ responder port least lane: D7-D0: */
3989+ /* D7-D0 */ TME_BUS_LANE_ABORT,
3990+ /* D15-D8 */ TME_BUS_LANE_ABORT,
3991+ /* D23-D16 */ TME_BUS_LANE_ABORT,
3992+ /* D31-D24 */ TME_BUS_LANE_ABORT,
3993+
3994+ /* initiator maximum cycle size: 32 bits
3995+ initiator address offset: 8 bits
3996+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
3997+ responder bus port size: 16 bits
3998+ responder port least lane: D15-D8: */
3999+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4000+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4001+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4002+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4003+
4004+ /* initiator maximum cycle size: 32 bits
4005+ initiator address offset: 8 bits
4006+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
4007+ responder bus port size: 16 bits
4008+ responder port least lane: D23-D16: */
4009+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4010+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4011+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4012+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4013+
4014+ /* initiator maximum cycle size: 32 bits
4015+ initiator address offset: 8 bits
4016+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
4017+ responder bus port size: 16 bits
4018+ responder port least lane: D31-D24
4019+ (responder port not correctly positioned for this initiator): */
4020+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4021+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4022+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4023+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4024+
4025+ /* initiator maximum cycle size: 32 bits
4026+ initiator address offset: 8 bits
4027+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
4028+ responder bus port size: 32 bits
4029+ responder port least lane: D7-D0: */
4030+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4031+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4032+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4033+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4034+
4035+ /* initiator maximum cycle size: 32 bits
4036+ initiator address offset: 8 bits
4037+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
4038+ responder bus port size: 32 bits
4039+ responder port least lane: D15-D8
4040+ (responder port not correctly positioned for this initiator): */
4041+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4042+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4043+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4044+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4045+
4046+ /* initiator maximum cycle size: 32 bits
4047+ initiator address offset: 8 bits
4048+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
4049+ responder bus port size: 32 bits
4050+ responder port least lane: D23-D16
4051+ (responder port not correctly positioned for this initiator): */
4052+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4053+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4054+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4055+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4056+
4057+ /* initiator maximum cycle size: 32 bits
4058+ initiator address offset: 8 bits
4059+ (a 32-bit initiator cannot request 32 bits at an 8-bit offset - this is an array placeholder)
4060+ responder bus port size: 32 bits
4061+ responder port least lane: D31-D24
4062+ (responder port not correctly positioned for this initiator): */
4063+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4064+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4065+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4066+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4067+
4068+ /* initiator maximum cycle size: 32 bits
4069+ initiator address offset: 16 bits
4070+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4071+ responder bus port size: 8 bits
4072+ responder port least lane: D7-D0: */
4073+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4074+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4075+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4076+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4077+
4078+ /* initiator maximum cycle size: 32 bits
4079+ initiator address offset: 16 bits
4080+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4081+ responder bus port size: 8 bits
4082+ responder port least lane: D15-D8: */
4083+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4084+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4085+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4086+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4087+
4088+ /* initiator maximum cycle size: 32 bits
4089+ initiator address offset: 16 bits
4090+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4091+ responder bus port size: 8 bits
4092+ responder port least lane: D23-D16: */
4093+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4094+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4095+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4096+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4097+
4098+ /* initiator maximum cycle size: 32 bits
4099+ initiator address offset: 16 bits
4100+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4101+ responder bus port size: 8 bits
4102+ responder port least lane: D31-D24: */
4103+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4104+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4105+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4106+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4107+
4108+ /* initiator maximum cycle size: 32 bits
4109+ initiator address offset: 16 bits
4110+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4111+ responder bus port size: 16 bits
4112+ responder port least lane: D7-D0: */
4113+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4114+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4115+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4116+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4117+
4118+ /* initiator maximum cycle size: 32 bits
4119+ initiator address offset: 16 bits
4120+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4121+ responder bus port size: 16 bits
4122+ responder port least lane: D15-D8: */
4123+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4124+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4125+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4126+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4127+
4128+ /* initiator maximum cycle size: 32 bits
4129+ initiator address offset: 16 bits
4130+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4131+ responder bus port size: 16 bits
4132+ responder port least lane: D23-D16: */
4133+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4134+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4135+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4136+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4137+
4138+ /* initiator maximum cycle size: 32 bits
4139+ initiator address offset: 16 bits
4140+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4141+ responder bus port size: 16 bits
4142+ responder port least lane: D31-D24
4143+ (responder port not correctly positioned for this initiator): */
4144+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4145+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4146+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4147+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4148+
4149+ /* initiator maximum cycle size: 32 bits
4150+ initiator address offset: 16 bits
4151+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4152+ responder bus port size: 32 bits
4153+ responder port least lane: D7-D0: */
4154+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4155+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4156+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4157+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4158+
4159+ /* initiator maximum cycle size: 32 bits
4160+ initiator address offset: 16 bits
4161+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4162+ responder bus port size: 32 bits
4163+ responder port least lane: D15-D8
4164+ (responder port not correctly positioned for this initiator): */
4165+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4166+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4167+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4168+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4169+
4170+ /* initiator maximum cycle size: 32 bits
4171+ initiator address offset: 16 bits
4172+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4173+ responder bus port size: 32 bits
4174+ responder port least lane: D23-D16
4175+ (responder port not correctly positioned for this initiator): */
4176+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4177+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4178+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4179+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4180+
4181+ /* initiator maximum cycle size: 32 bits
4182+ initiator address offset: 16 bits
4183+ (a 32-bit initiator cannot request 32 bits at an 16-bit offset - this is an array placeholder)
4184+ responder bus port size: 32 bits
4185+ responder port least lane: D31-D24
4186+ (responder port not correctly positioned for this initiator): */
4187+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4188+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4189+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4190+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4191+
4192+ /* initiator maximum cycle size: 32 bits
4193+ initiator address offset: 24 bits
4194+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4195+ responder bus port size: 8 bits
4196+ responder port least lane: D7-D0: */
4197+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4198+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4199+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4200+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4201+
4202+ /* initiator maximum cycle size: 32 bits
4203+ initiator address offset: 24 bits
4204+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4205+ responder bus port size: 8 bits
4206+ responder port least lane: D15-D8: */
4207+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4208+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4209+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4210+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4211+
4212+ /* initiator maximum cycle size: 32 bits
4213+ initiator address offset: 24 bits
4214+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4215+ responder bus port size: 8 bits
4216+ responder port least lane: D23-D16: */
4217+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4218+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4219+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4220+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4221+
4222+ /* initiator maximum cycle size: 32 bits
4223+ initiator address offset: 24 bits
4224+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4225+ responder bus port size: 8 bits
4226+ responder port least lane: D31-D24: */
4227+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4228+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4229+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4230+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4231+
4232+ /* initiator maximum cycle size: 32 bits
4233+ initiator address offset: 24 bits
4234+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4235+ responder bus port size: 16 bits
4236+ responder port least lane: D7-D0: */
4237+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4238+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4239+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4240+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4241+
4242+ /* initiator maximum cycle size: 32 bits
4243+ initiator address offset: 24 bits
4244+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4245+ responder bus port size: 16 bits
4246+ responder port least lane: D15-D8: */
4247+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4248+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4249+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4250+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4251+
4252+ /* initiator maximum cycle size: 32 bits
4253+ initiator address offset: 24 bits
4254+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4255+ responder bus port size: 16 bits
4256+ responder port least lane: D23-D16: */
4257+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4258+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4259+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4260+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4261+
4262+ /* initiator maximum cycle size: 32 bits
4263+ initiator address offset: 24 bits
4264+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4265+ responder bus port size: 16 bits
4266+ responder port least lane: D31-D24
4267+ (responder port not correctly positioned for this initiator): */
4268+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4269+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4270+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4271+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4272+
4273+ /* initiator maximum cycle size: 32 bits
4274+ initiator address offset: 24 bits
4275+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4276+ responder bus port size: 32 bits
4277+ responder port least lane: D7-D0: */
4278+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4279+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4280+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4281+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4282+
4283+ /* initiator maximum cycle size: 32 bits
4284+ initiator address offset: 24 bits
4285+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4286+ responder bus port size: 32 bits
4287+ responder port least lane: D15-D8
4288+ (responder port not correctly positioned for this initiator): */
4289+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4290+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4291+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4292+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4293+
4294+ /* initiator maximum cycle size: 32 bits
4295+ initiator address offset: 24 bits
4296+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4297+ responder bus port size: 32 bits
4298+ responder port least lane: D23-D16
4299+ (responder port not correctly positioned for this initiator): */
4300+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4301+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4302+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4303+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4304+
4305+ /* initiator maximum cycle size: 32 bits
4306+ initiator address offset: 24 bits
4307+ (a 32-bit initiator cannot request 32 bits at an 24-bit offset - this is an array placeholder)
4308+ responder bus port size: 32 bits
4309+ responder port least lane: D31-D24
4310+ (responder port not correctly positioned for this initiator): */
4311+ /* D7-D0 */ TME_BUS_LANE_ABORT,
4312+ /* D15-D8 */ TME_BUS_LANE_ABORT,
4313+ /* D23-D16 */ TME_BUS_LANE_ABORT,
4314+ /* D31-D24 */ TME_BUS_LANE_ABORT,
4315+};
4316+
4317+/* the 32-bit bus master DMA read function: */
4318+int
4319+tme_bus_device_dma_read_32(struct tme_bus_device *bus_device,
4320+ tme_bus_addr_t address_init,
4321+ tme_bus_addr_t size,
4322+ tme_uint8_t *buffer,
4323+ unsigned int locks)
4324+{
4325+ struct tme_bus_tlb *tlb, tlb_local;
4326+ struct tme_bus_connection *conn_bus;
4327+ tme_bus_addr_t count_minus_one, count;
4328+ struct tme_bus_cycle cycle;
4329+ tme_bus_addr_t address_resp;
4330+ int shift;
4331+ int err;
4332+
4333+ /* assume no error: */
4334+ err = TME_OK;
4335+
4336+ /* loop while we have more bytes to read: */
4337+ for (; err == TME_OK && size > 0; ) {
4338+
4339+ /* hash this address into a TLB entry: */
4340+ tlb = (*bus_device->tme_bus_device_tlb_hash)
4341+ (bus_device,
4342+ address_init,
4343+ TME_BUS_CYCLE_READ);
4344+
4345+ /* busy this TLB entry: */
4346+ tme_bus_tlb_busy(tlb);
4347+
4348+ /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't
4349+ allow reading, reload it: */
4350+ if (tme_bus_tlb_is_invalid(tlb)
4351+ || address_init < tlb->tme_bus_tlb_addr_first
4352+ || address_init > tlb->tme_bus_tlb_addr_last
4353+ || (tlb->tme_bus_tlb_emulator_off_read == TME_EMULATOR_OFF_UNDEF
4354+ && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_READ))) {
4355+
4356+ /* unbusy this TLB entry for filling: */
4357+ tme_bus_tlb_unbusy_fill(tlb);
4358+
4359+ /* pass this TLB's token: */
4360+ tlb_local.tme_bus_tlb_token = tlb->tme_bus_tlb_token;
4361+
4362+ /* get our bus connection: */
4363+ conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *,
4364+ bus_device->tme_bus_device_connection,
4365+ &bus_device->tme_bus_device_connection_rwlock);
4366+
4367+ /* unlock the device: */
4368+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
4369+
4370+ /* reload the TLB entry: */
4371+ err = (*conn_bus->tme_bus_tlb_fill)
4372+ (conn_bus,
4373+ &tlb_local,
4374+ address_init,
4375+ TME_BUS_CYCLE_READ);
4376+
4377+ /* lock the device: */
4378+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
4379+
4380+ /* return if we couldn't fill the TLB entry: */
4381+ if (err != TME_OK) {
4382+ return (err);
4383+ }
4384+
4385+ /* store the TLB entry: */
4386+ *tlb = tlb_local;
4387+
4388+ /* loop to check the newly filled TLB entry: */
4389+ continue;
4390+ }
4391+
4392+ /* if this TLB entry allows fast reading: */
4393+ if (tlb->tme_bus_tlb_emulator_off_read != TME_EMULATOR_OFF_UNDEF) {
4394+
4395+ /* see how many bytes we can fast read from this TLB entry,
4396+ starting at this address: */
4397+ count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init);
4398+
4399+ /* read that many bytes or size bytes, whichever is smaller: */
4400+ count_minus_one = TME_MIN(count_minus_one,
4401+ (size - 1));
4402+ count = count_minus_one + 1;
4403+ assert (count != 0);
4404+
4405+ /* do the bus read: */
4406+ tme_memory_bus_read_buffer((tlb->tme_bus_tlb_emulator_off_read + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint32_t));
4407+
4408+ /* unbusy this TLB entry: */
4409+ tme_bus_tlb_unbusy(tlb);
4410+ }
4411+
4412+ /* otherwise, we have to do a slow read: */
4413+ else {
4414+
4415+ /* get the size of this bus cycle: */
4416+ count = (1 << TME_BUS32_LOG2);
4417+ count -= (address_init & (count - 1));
4418+ count = TME_MIN(count, size);
4419+
4420+ /* fill the cycle structure: */
4421+ cycle.tme_bus_cycle_type = TME_BUS_CYCLE_READ;
4422+ cycle.tme_bus_cycle_size = count;
4423+ cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */
4424+ cycle.tme_bus_cycle_buffer_increment = 1;
4425+ cycle.tme_bus_cycle_lane_routing
4426+ = (bus_device->tme_bus_device_router
4427+ + TME_BUS_ROUTER_INIT_INDEX(TME_BUS32_LOG2, count, address_init));
4428+
4429+ /* XXX this should come from a socket configuration: */
4430+ cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS32_LOG2);
4431+
4432+ /* form the physical address for the bus cycle handler: */
4433+ address_resp = tlb->tme_bus_tlb_addr_offset + address_init;
4434+ shift = tlb->tme_bus_tlb_addr_shift;
4435+ if (shift < 0) {
4436+ address_resp <<= (0 - shift);
4437+ }
4438+ else if (shift > 0) {
4439+ address_resp >>= shift;
4440+ }
4441+ cycle.tme_bus_cycle_address = address_resp;
4442+
4443+ /* unbusy this TLB entry: */
4444+ tme_bus_tlb_unbusy(tlb);
4445+
4446+ /* unlock the device: */
4447+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
4448+
4449+ /* run the bus cycle: */
4450+ err = (*tlb->tme_bus_tlb_cycle)
4451+ (tlb->tme_bus_tlb_cycle_private, &cycle);
4452+
4453+ /* if the TLB entry was invalidated before the read: */
4454+ if (err == EBADF
4455+ && tme_bus_tlb_is_invalid(tlb)) {
4456+ count = 0;
4457+ }
4458+
4459+ /* otherwise, any other error might be a bus error: */
4460+ else if (err != TME_OK) {
4461+ err = tme_bus_tlb_fault(tlb, &cycle, err);
4462+ assert (err != TME_OK);
4463+ }
4464+
4465+ /* lock the device: */
4466+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
4467+ }
4468+
4469+ /* update the address, buffer, and size and continue: */
4470+ address_init += count;
4471+ buffer += count;
4472+ size -= count;
4473+ }
4474+
4475+ return (err);
4476+}
4477+
4478+/* the 32-bit bus master DMA write function: */
4479+int
4480+tme_bus_device_dma_write_32(struct tme_bus_device *bus_device,
4481+ tme_bus_addr_t address_init,
4482+ tme_bus_addr_t size,
4483+ const tme_uint8_t *buffer,
4484+ unsigned int locks)
4485+{
4486+ struct tme_bus_tlb *tlb, tlb_local;
4487+ struct tme_bus_connection *conn_bus;
4488+ tme_bus_addr_t count_minus_one, count;
4489+ struct tme_bus_cycle cycle;
4490+ tme_bus_addr_t address_resp;
4491+ int shift;
4492+ int err;
4493+
4494+ /* assume no error: */
4495+ err = TME_OK;
4496+
4497+ /* loop while we have more bytes to write: */
4498+ for (; err == TME_OK && size > 0; ) {
4499+
4500+ /* hash this address into a TLB entry: */
4501+ tlb = (*bus_device->tme_bus_device_tlb_hash)
4502+ (bus_device,
4503+ address_init,
4504+ TME_BUS_CYCLE_WRITE);
4505+
4506+ /* busy this TLB entry: */
4507+ tme_bus_tlb_busy(tlb);
4508+
4509+ /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't
4510+ allow writing, reload it: */
4511+ if (tme_bus_tlb_is_invalid(tlb)
4512+ || address_init < tlb->tme_bus_tlb_addr_first
4513+ || address_init > tlb->tme_bus_tlb_addr_last
4514+ || (tlb->tme_bus_tlb_emulator_off_write == TME_EMULATOR_OFF_UNDEF
4515+ && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_WRITE))) {
4516+
4517+ /* unbusy this TLB entry for filling: */
4518+ tme_bus_tlb_unbusy_fill(tlb);
4519+
4520+ /* pass this TLB's token: */
4521+ tlb_local.tme_bus_tlb_token = tlb->tme_bus_tlb_token;
4522+
4523+ /* get our bus connection: */
4524+ conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *,
4525+ bus_device->tme_bus_device_connection,
4526+ &bus_device->tme_bus_device_connection_rwlock);
4527+
4528+ /* unlock the device: */
4529+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
4530+
4531+ /* reload the TLB entry: */
4532+ err = (*conn_bus->tme_bus_tlb_fill)
4533+ (conn_bus,
4534+ &tlb_local,
4535+ address_init,
4536+ TME_BUS_CYCLE_WRITE);
4537+
4538+ /* lock the device: */
4539+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
4540+
4541+ /* return if we couldn't fill the TLB entry: */
4542+ if (err != TME_OK) {
4543+ return (err);
4544+ }
4545+
4546+ /* store the TLB entry: */
4547+ *tlb = tlb_local;
4548+
4549+ /* loop to check the newly filled TLB entry: */
4550+ continue;
4551+ }
4552+
4553+ /* if this TLB entry allows fast writing: */
4554+ if (tlb->tme_bus_tlb_emulator_off_write != TME_EMULATOR_OFF_UNDEF) {
4555+
4556+ /* see how many bytes we can fast write to this TLB entry,
4557+ starting at this address: */
4558+ count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init);
4559+
4560+ /* write that many bytes or size bytes, whichever is smaller: */
4561+ count_minus_one = TME_MIN(count_minus_one,
4562+ (size - 1));
4563+ count = count_minus_one + 1;
4564+ assert (count != 0);
4565+
4566+ /* do the bus write: */
4567+ tme_memory_bus_write_buffer((tlb->tme_bus_tlb_emulator_off_write + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint32_t));
4568+
4569+ /* unbusy this TLB entry: */
4570+ tme_bus_tlb_unbusy(tlb);
4571+ }
4572+
4573+ /* otherwise, we have to do a slow write: */
4574+ else {
4575+
4576+ /* get the size of this bus cycle: */
4577+ count = (1 << TME_BUS32_LOG2);
4578+ count -= (address_init & (count - 1));
4579+ count = TME_MIN(count, size);
4580+
4581+ /* fill the cycle structure: */
4582+ cycle.tme_bus_cycle_type = TME_BUS_CYCLE_WRITE;
4583+ cycle.tme_bus_cycle_size = count;
4584+ cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */
4585+ cycle.tme_bus_cycle_buffer_increment = 1;
4586+ cycle.tme_bus_cycle_lane_routing
4587+ = (bus_device->tme_bus_device_router
4588+ + TME_BUS_ROUTER_INIT_INDEX(TME_BUS32_LOG2, count, address_init));
4589+
4590+ /* XXX this should come from a socket configuration: */
4591+ cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS32_LOG2);
4592+
4593+ /* form the physical address for the bus cycle handler: */
4594+ address_resp = tlb->tme_bus_tlb_addr_offset + address_init;
4595+ shift = tlb->tme_bus_tlb_addr_shift;
4596+ if (shift < 0) {
4597+ address_resp <<= (0 - shift);
4598+ }
4599+ else if (shift > 0) {
4600+ address_resp >>= shift;
4601+ }
4602+ cycle.tme_bus_cycle_address = address_resp;
4603+
4604+ /* unbusy this TLB entry: */
4605+ tme_bus_tlb_unbusy(tlb);
4606+
4607+ /* unlock the device: */
4608+ (*bus_device->tme_bus_device_unlock)(bus_device, locks);
4609+
4610+ /* run the bus cycle: */
4611+ err = (*tlb->tme_bus_tlb_cycle)
4612+ (tlb->tme_bus_tlb_cycle_private, &cycle);
4613+
4614+ /* if the TLB entry was invalidated before the write: */
4615+ if (err == EBADF
4616+ && tme_bus_tlb_is_invalid(tlb)) {
4617+ count = 0;
4618+ }
4619+
4620+ /* otherwise, any other error might be a bus error: */
4621+ else if (err != TME_OK) {
4622+ err = tme_bus_tlb_fault(tlb, &cycle, err);
4623+ assert (err != TME_OK);
4624+ }
4625+
4626+ /* lock the device: */
4627+ (*bus_device->tme_bus_device_lock)(bus_device, locks);
4628+ }
4629+
4630+ /* update the address, buffer, and size and continue: */
4631+ address_init += count;
4632+ buffer += count;
4633+ size -= count;
4634+ }
4635+
4636+ return (err);
4637+}
--- /dev/null
+++ b/generic/bus-device-auto.sh
@@ -0,0 +1,665 @@
1+#! /bin/sh
2+# Generated from ../../generic/bus-device-auto.m4 by GNU Autoconf 2.69.
3+## -------------------- ##
4+## M4sh Initialization. ##
5+## -------------------- ##
6+
7+# Be more Bourne compatible
8+DUALCASE=1; export DUALCASE # for MKS sh
9+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
10+ emulate sh
11+ NULLCMD=:
12+ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
13+ # is contrary to our usage. Disable this feature.
14+ alias -g '${1+"$@"}'='"$@"'
15+ setopt NO_GLOB_SUBST
16+else
17+ case `(set -o) 2>/dev/null` in #(
18+ *posix*) :
19+ set -o posix ;; #(
20+ *) :
21+ ;;
22+esac
23+fi
24+
25+
26+as_nl='
27+'
28+export as_nl
29+# Printing a long string crashes Solaris 7 /usr/bin/printf.
30+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
31+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
32+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
33+# Prefer a ksh shell builtin over an external printf program on Solaris,
34+# but without wasting forks for bash or zsh.
35+if test -z "$BASH_VERSION$ZSH_VERSION" \
36+ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
37+ as_echo='print -r --'
38+ as_echo_n='print -rn --'
39+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
40+ as_echo='printf %s\n'
41+ as_echo_n='printf %s'
42+else
43+ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
44+ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
45+ as_echo_n='/usr/ucb/echo -n'
46+ else
47+ as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
48+ as_echo_n_body='eval
49+ arg=$1;
50+ case $arg in #(
51+ *"$as_nl"*)
52+ expr "X$arg" : "X\\(.*\\)$as_nl";
53+ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
54+ esac;
55+ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
56+ '
57+ export as_echo_n_body
58+ as_echo_n='sh -c $as_echo_n_body as_echo'
59+ fi
60+ export as_echo_body
61+ as_echo='sh -c $as_echo_body as_echo'
62+fi
63+
64+# The user is always right.
65+if test "${PATH_SEPARATOR+set}" != set; then
66+ PATH_SEPARATOR=:
67+ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
68+ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
69+ PATH_SEPARATOR=';'
70+ }
71+fi
72+
73+
74+# IFS
75+# We need space, tab and new line, in precisely that order. Quoting is
76+# there to prevent editors from complaining about space-tab.
77+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
78+# splitting by setting IFS to empty value.)
79+IFS=" "" $as_nl"
80+
81+# Find who we are. Look in the path if we contain no directory separator.
82+as_myself=
83+case $0 in #((
84+ *[\\/]* ) as_myself=$0 ;;
85+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
86+for as_dir in $PATH
87+do
88+ IFS=$as_save_IFS
89+ test -z "$as_dir" && as_dir=.
90+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
91+ done
92+IFS=$as_save_IFS
93+
94+ ;;
95+esac
96+# We did not find ourselves, most probably we were run as `sh COMMAND'
97+# in which case we are not to be found in the path.
98+if test "x$as_myself" = x; then
99+ as_myself=$0
100+fi
101+if test ! -f "$as_myself"; then
102+ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
103+ exit 1
104+fi
105+
106+# Unset variables that we do not need and which cause bugs (e.g. in
107+# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
108+# suppresses any "Segmentation fault" message there. '((' could
109+# trigger a bug in pdksh 5.2.14.
110+for as_var in BASH_ENV ENV MAIL MAILPATH
111+do eval test x\${$as_var+set} = xset \
112+ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
113+done
114+PS1='$ '
115+PS2='> '
116+PS4='+ '
117+
118+# NLS nuisances.
119+LC_ALL=C
120+export LC_ALL
121+LANGUAGE=C
122+export LANGUAGE
123+
124+# CDPATH.
125+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
126+
127+if test "x$CONFIG_SHELL" = x; then
128+ as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then :
129+ emulate sh
130+ NULLCMD=:
131+ # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which
132+ # is contrary to our usage. Disable this feature.
133+ alias -g '\${1+\"\$@\"}'='\"\$@\"'
134+ setopt NO_GLOB_SUBST
135+else
136+ case \`(set -o) 2>/dev/null\` in #(
137+ *posix*) :
138+ set -o posix ;; #(
139+ *) :
140+ ;;
141+esac
142+fi
143+"
144+ as_required="as_fn_return () { (exit \$1); }
145+as_fn_success () { as_fn_return 0; }
146+as_fn_failure () { as_fn_return 1; }
147+as_fn_ret_success () { return 0; }
148+as_fn_ret_failure () { return 1; }
149+
150+exitcode=0
151+as_fn_success || { exitcode=1; echo as_fn_success failed.; }
152+as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; }
153+as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; }
154+as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; }
155+if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then :
156+
157+else
158+ exitcode=1; echo positional parameters were not saved.
159+fi
160+test x\$exitcode = x0 || exit 1
161+test -x / || exit 1"
162+ as_suggested=""
163+ if (eval "$as_required") 2>/dev/null; then :
164+ as_have_required=yes
165+else
166+ as_have_required=no
167+fi
168+ if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then :
169+
170+else
171+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
172+as_found=false
173+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
174+do
175+ IFS=$as_save_IFS
176+ test -z "$as_dir" && as_dir=.
177+ as_found=:
178+ case $as_dir in #(
179+ /*)
180+ for as_base in sh bash ksh sh5; do
181+ # Try only shells that exist, to save several forks.
182+ as_shell=$as_dir/$as_base
183+ if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
184+ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then :
185+ CONFIG_SHELL=$as_shell as_have_required=yes
186+ break 2
187+fi
188+ done;;
189+ esac
190+ as_found=false
191+done
192+$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } &&
193+ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then :
194+ CONFIG_SHELL=$SHELL as_have_required=yes
195+fi; }
196+IFS=$as_save_IFS
197+
198+
199+ if test "x$CONFIG_SHELL" != x; then :
200+ export CONFIG_SHELL
201+ # We cannot yet assume a decent shell, so we have to provide a
202+# neutralization value for shells without unset; and this also
203+# works around shells that cannot unset nonexistent variables.
204+# Preserve -v and -x to the replacement shell.
205+BASH_ENV=/dev/null
206+ENV=/dev/null
207+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
208+case $- in # ((((
209+ *v*x* | *x*v* ) as_opts=-vx ;;
210+ *v* ) as_opts=-v ;;
211+ *x* ) as_opts=-x ;;
212+ * ) as_opts= ;;
213+esac
214+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
215+# Admittedly, this is quite paranoid, since all the known shells bail
216+# out after a failed `exec'.
217+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
218+exit 255
219+fi
220+
221+ if test x$as_have_required = xno; then :
222+ $as_echo "$0: This script requires a shell more modern than all"
223+ $as_echo "$0: the shells that I found on your system."
224+ if test x${ZSH_VERSION+set} = xset ; then
225+ $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should"
226+ $as_echo "$0: be upgraded to zsh 4.3.4 or later."
227+ else
228+ $as_echo "$0: Please tell bug-autoconf@gnu.org about your system,
229+$0: including any error possibly output before this
230+$0: message. Then install a modern shell, or manually run
231+$0: the script under such a shell if you do have one."
232+ fi
233+ exit 1
234+fi
235+fi
236+fi
237+SHELL=${CONFIG_SHELL-/bin/sh}
238+export SHELL
239+# Unset more variables known to interfere with behavior of common tools.
240+CLICOLOR_FORCE= GREP_OPTIONS=
241+unset CLICOLOR_FORCE GREP_OPTIONS
242+
243+## --------------------- ##
244+## M4sh Shell Functions. ##
245+## --------------------- ##
246+# as_fn_unset VAR
247+# ---------------
248+# Portably unset VAR.
249+as_fn_unset ()
250+{
251+ { eval $1=; unset $1;}
252+}
253+as_unset=as_fn_unset
254+## -------------------- ##
255+## Main body of script. ##
256+## -------------------- ##
257+
258+
259+# $Id: bus-device-auto.sh,v 1.3 2009/08/29 17:52:04 fredette Exp $
260+
261+# generic/bus-device-auto.sh - automatically generates C code for
262+# generic bus device support:
263+
264+#
265+# Copyright (c) 2004 Matt Fredette
266+# All rights reserved.
267+#
268+# Redistribution and use in source and binary forms, with or without
269+# modification, are permitted provided that the following conditions
270+# are met:
271+# 1. Redistributions of source code must retain the above copyright
272+# notice, this list of conditions and the following disclaimer.
273+# 2. Redistributions in binary form must reproduce the above copyright
274+# notice, this list of conditions and the following disclaimer in the
275+# documentation and/or other materials provided with the distribution.
276+# 3. All advertising materials mentioning features or use of this software
277+# must display the following acknowledgement:
278+# This product includes software developed by Matt Fredette.
279+# 4. The name of the author may not be used to endorse or promote products
280+# derived from this software without specific prior written permission.
281+#
282+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
283+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
284+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
285+# DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
286+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
287+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
288+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
289+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
290+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
291+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
292+# POSSIBILITY OF SUCH DAMAGE.
293+#
294+
295+header=false
296+
297+for option
298+do
299+ case $option in
300+ --header) header=true ;;
301+ esac
302+done
303+
304+PROG=`basename $0`
305+cat <<EOF
306+/* automatically generated by $PROG, do not edit! */
307+_TME_RCSID("\$Id: bus-device-auto.sh,v 1.3 2009/08/29 17:52:04 fredette Exp $");
308+EOF
309+
310+if $header; then :; else
311+ cat <<EOF
312+
313+/* this gives the number of entries that must be in a generic bus
314+ router array for a device with a bus size of 8 * (2 ^ siz_lg2)
315+ bits: */
316+#define TME_BUS_ROUTER_INIT_SIZE(siz_lg2) \\
317+ TME_BUS_ROUTER_INIT_INDEX(siz_lg2, (1 << (siz_lg2)) + 1, 0)
318+
319+EOF
320+fi
321+
322+# permute over initiator bus port width:
323+#
324+i_width=8
325+while test ${i_width} != 32; do
326+ i_width=`expr ${i_width} \* 2`
327+
328+ # permute over initiator endianness:
329+ #
330+ for endian in b l; do
331+ if test ${endian} = b; then endian_what=big; else endian_what=little; fi
332+
333+ # start the array:
334+ #
335+ $as_echo ""
336+ $as_echo "/* the ${i_width}-bit ${endian_what}-endian bus master bus router: */"
337+ what="const tme_bus_lane_t tme_bus_device_router_${i_width}e${endian}"
338+ if $header; then
339+ $as_echo "extern ${what}[];"
340+ continue
341+ fi
342+ $as_echo "${what}[TME_BUS_ROUTER_INIT_SIZE(TME_BUS${i_width}_LOG2)] = {"
343+
344+ # permute over initiator maximum cycle size:
345+ #
346+ i_size=0
347+ while test `expr ${i_size} \< ${i_width}` = 1; do
348+ i_size=`expr ${i_size} + 8`
349+
350+ # permute over initiator address offset:
351+ #
352+ i_offset=0
353+ while test `expr ${i_offset} \< ${i_width}` = 1; do
354+
355+ # calculate the initiator least and greatest lanes:
356+ #
357+ placeholder=false
358+ if test ${endian} = b; then
359+ i_lane_greatest=`expr 0 - 8 + ${i_width} - ${i_offset}`
360+ i_lane_least=`expr 8 + \( ${i_lane_greatest} \) - ${i_size}`
361+ if test `expr \( ${i_lane_least} \) \< 0` = 1; then
362+ placeholder=true
363+ fi
364+ else
365+ i_lane_least=$i_offset
366+ i_lane_greatest=`expr 0 - 8 + ${i_offset} + ${i_size}`
367+ if test `expr \( ${i_lane_greatest} \) \>= ${i_width}` = 1; then
368+ placeholder=true
369+ fi
370+ fi
371+
372+ # permute over responder bus port width:
373+ #
374+ r_width=4
375+ while test `expr ${r_width} \< ${i_width}` = 1; do
376+ r_width=`expr ${r_width} \* 2`
377+
378+ # permute over responder bus port least lane:
379+ #
380+ r_lane_least=0
381+ while test `expr ${r_lane_least} \< ${i_width}` = 1; do
382+ r_lane_greatest=`expr 0 - 8 + ${r_lane_least} + ${r_width}`
383+
384+ # emit the initiator information:
385+ #
386+ $as_echo ""
387+ $as_echo " /* initiator maximum cycle size: ${i_size} bits"
388+ $as_echo " initiator address offset: ${i_offset} bits"
389+ if $placeholder; then
390+ $as_echo " (a ${i_width}-bit initiator cannot request ${i_size} bits at an ${i_offset}-bit offset - this is an array placeholder)"
391+ fi
392+
393+ # emit the responder information:
394+ #
395+ $as_echo " responder bus port size: ${r_width} bits"
396+ $as_echo_n " responder port least lane: D"`expr ${r_lane_least} + 7`"-D${r_lane_least}"
397+
398+ # if the responder bus port greatest lane is
399+ # greater than the initiator bus port width,
400+ # part of the responder's port is outside of
401+ # the initiator's port:
402+ #
403+ if test `expr \( ${r_lane_greatest} \) \>= ${i_width}` = 1; then
404+ $as_echo ""
405+ $as_echo_n " (responder port not correctly positioned for this initiator)"
406+ fi
407+ $as_echo ": */"
408+
409+ # permute over the lanes:
410+ #
411+ lane=0
412+ if test ${endian} = b; then
413+ route=`expr ${i_size} / 8`
414+ route_increment=-1
415+ else
416+ route=-1
417+ route_increment=1
418+ fi
419+ while test `expr ${lane} \< ${i_width}` = 1; do
420+ $as_echo_n " /* D"`expr ${lane} + 7`"-D${lane} */ "
421+
422+ # see if this lane is on in the responder:
423+ #
424+ if test `expr ${lane} \>= ${r_lane_least}` = 1 \
425+ && test `expr ${lane} \<= \( ${r_lane_greatest} \)` = 1; then
426+ r_lane_on=true
427+ else
428+ r_lane_on=false
429+ fi
430+
431+ # see if this lane is on in the initiator:
432+ #
433+ if test `expr ${lane} \>= \( ${i_lane_least} \)` = 1 \
434+ && test `expr ${lane} \<= \( ${i_lane_greatest} \)` = 1; then
435+ i_lane_on=true
436+ route=`expr \( ${route} + ${route_increment} \)`
437+ else
438+ i_lane_on=false
439+ fi
440+
441+ # if this is a placeholder entry:
442+ #
443+ if $placeholder; then
444+ $as_echo_n "TME_BUS_LANE_ABORT"
445+
446+ # otherwise, this is a real entry:
447+ #
448+ else
449+ if $i_lane_on; then
450+ $as_echo_n "TME_BUS_LANE_ROUTE(${route})"
451+ if $r_lane_on; then :; else
452+ $as_echo_n " | TME_BUS_LANE_WARN"
453+ fi
454+ else
455+ $as_echo_n "TME_BUS_LANE_UNDEF"
456+ fi
457+ fi
458+
459+ $as_echo ","
460+ lane=`expr ${lane} + 8`
461+ done
462+
463+ r_lane_least=`expr ${r_lane_least} + 8`
464+ done
465+ done
466+
467+ i_offset=`expr ${i_offset} + 8`
468+ done
469+ done
470+
471+ # finish the array:
472+ #
473+ $as_echo "};"
474+ done
475+
476+ # permute over read/write:
477+ #
478+ for name in read write; do
479+ capname=`$as_echo $name | tr a-z A-Z`
480+ if test $name = read; then
481+ naming="reading"
482+ from="from"
483+ constbuffer=""
484+ else
485+ naming="writing"
486+ from="to"
487+ constbuffer="const "
488+ fi
489+
490+ $as_echo ""
491+ $as_echo "/* the ${i_width}-bit bus master DMA ${name} function: */"
492+ if $header; then
493+ $as_echo "int tme_bus_device_dma_${name}_${i_width} _TME_P((struct tme_bus_device *,"
494+ $as_echo " tme_bus_addr_t,"
495+ $as_echo " tme_bus_addr_t,"
496+ $as_echo " ${constbuffer}tme_uint8_t *,"
497+ $as_echo " unsigned int));"
498+ continue
499+ fi
500+ $as_echo "int"
501+ $as_echo "tme_bus_device_dma_${name}_${i_width}(struct tme_bus_device *bus_device,"
502+ $as_echo " tme_bus_addr_t address_init,"
503+ $as_echo " tme_bus_addr_t size,"
504+ $as_echo " ${constbuffer}tme_uint8_t *buffer,"
505+ $as_echo " unsigned int locks)"
506+ $as_echo "{"
507+ $as_echo " struct tme_bus_tlb *tlb, tlb_local;"
508+ $as_echo " struct tme_bus_connection *conn_bus;"
509+ $as_echo " tme_bus_addr_t count_minus_one, count;"
510+ $as_echo " struct tme_bus_cycle cycle;"
511+ $as_echo " tme_bus_addr_t address_resp;"
512+ $as_echo " int shift;"
513+ $as_echo " int err;"
514+ $as_echo ""
515+ $as_echo " /* assume no error: */"
516+ $as_echo " err = TME_OK;"
517+ $as_echo ""
518+ $as_echo " /* loop while we have more bytes to ${name}: */"
519+ $as_echo " for (; err == TME_OK && size > 0; ) {"
520+ $as_echo ""
521+ $as_echo " /* hash this address into a TLB entry: */"
522+ $as_echo " tlb = (*bus_device->tme_bus_device_tlb_hash)"
523+ $as_echo " (bus_device,"
524+ $as_echo " address_init,"
525+ $as_echo " TME_BUS_CYCLE_${capname});"
526+ $as_echo ""
527+ $as_echo " /* busy this TLB entry: */"
528+ $as_echo " tme_bus_tlb_busy(tlb);"
529+ $as_echo ""
530+ $as_echo " /* if this TLB entry is invalid, doesn't cover this address, or if it doesn't"
531+ $as_echo " allow ${naming}, reload it: */"
532+ $as_echo " if (tme_bus_tlb_is_invalid(tlb)"
533+ $as_echo " || address_init < tlb->tme_bus_tlb_addr_first"
534+ $as_echo " || address_init > tlb->tme_bus_tlb_addr_last"
535+ $as_echo " || (tlb->tme_bus_tlb_emulator_off_${name} == TME_EMULATOR_OFF_UNDEF"
536+ $as_echo " && !(tlb->tme_bus_tlb_cycles_ok & TME_BUS_CYCLE_${capname}))) {"
537+ $as_echo ""
538+ $as_echo " /* unbusy this TLB entry for filling: */"
539+ $as_echo " tme_bus_tlb_unbusy_fill(tlb);"
540+ $as_echo ""
541+ $as_echo " /* pass this TLB's token: */"
542+ $as_echo " tlb_local.tme_bus_tlb_token = tlb->tme_bus_tlb_token;"
543+ $as_echo ""
544+ $as_echo " /* get our bus connection: */"
545+ $as_echo " conn_bus = tme_memory_atomic_pointer_read(struct tme_bus_connection *,"
546+ $as_echo " bus_device->tme_bus_device_connection,"
547+ $as_echo " &bus_device->tme_bus_device_connection_rwlock);"
548+ $as_echo ""
549+ $as_echo " /* unlock the device: */"
550+ $as_echo " (*bus_device->tme_bus_device_unlock)(bus_device, locks);"
551+ $as_echo ""
552+ $as_echo " /* reload the TLB entry: */"
553+ $as_echo " err = (*conn_bus->tme_bus_tlb_fill)"
554+ $as_echo " (conn_bus,"
555+ $as_echo " &tlb_local,"
556+ $as_echo " address_init,"
557+ $as_echo " TME_BUS_CYCLE_${capname});"
558+ $as_echo ""
559+ $as_echo " /* lock the device: */"
560+ $as_echo " (*bus_device->tme_bus_device_lock)(bus_device, locks);"
561+ $as_echo ""
562+ $as_echo " /* return if we couldn't fill the TLB entry: */"
563+ $as_echo " if (err != TME_OK) {"
564+ $as_echo " return (err);"
565+ $as_echo " }"
566+ $as_echo ""
567+ $as_echo " /* store the TLB entry: */"
568+ $as_echo " *tlb = tlb_local;"
569+ $as_echo ""
570+ $as_echo " /* loop to check the newly filled TLB entry: */"
571+ $as_echo " continue;"
572+ $as_echo " }"
573+ $as_echo ""
574+ $as_echo " /* if this TLB entry allows fast ${naming}: */"
575+ $as_echo " if (tlb->tme_bus_tlb_emulator_off_${name} != TME_EMULATOR_OFF_UNDEF) {"
576+ $as_echo ""
577+ $as_echo " /* see how many bytes we can fast ${name} ${from} this TLB entry,"
578+ $as_echo " starting at this address: */"
579+ $as_echo " count_minus_one = (tlb->tme_bus_tlb_addr_last - address_init);"
580+ $as_echo ""
581+ $as_echo " /* ${name} that many bytes or size bytes, whichever is smaller: */"
582+ $as_echo " count_minus_one = TME_MIN(count_minus_one,"
583+ $as_echo " (size - 1));"
584+ $as_echo " count = count_minus_one + 1;"
585+ $as_echo " assert (count != 0);"
586+ $as_echo ""
587+ $as_echo " /* do the bus ${name}: */"
588+ $as_echo " tme_memory_bus_${name}_buffer((tlb->tme_bus_tlb_emulator_off_${name} + address_init), buffer, count, tlb->tme_bus_tlb_rwlock, sizeof(tme_uint8_t), sizeof(tme_uint${i_width}_t));"
589+ $as_echo ""
590+ $as_echo " /* unbusy this TLB entry: */"
591+ $as_echo " tme_bus_tlb_unbusy(tlb);"
592+ $as_echo " }"
593+ $as_echo ""
594+ $as_echo " /* otherwise, we have to do a slow ${name}: */"
595+ $as_echo " else {"
596+ $as_echo ""
597+ $as_echo " /* get the size of this bus cycle: */"
598+ $as_echo " count = (1 << TME_BUS${i_width}_LOG2);"
599+ $as_echo " count -= (address_init & (count - 1));"
600+ $as_echo " count = TME_MIN(count, size);"
601+ $as_echo ""
602+ $as_echo " /* fill the cycle structure: */"
603+ $as_echo " cycle.tme_bus_cycle_type = TME_BUS_CYCLE_${capname};"
604+ $as_echo " cycle.tme_bus_cycle_size = count;"
605+ $as_echo " cycle.tme_bus_cycle_buffer = (tme_uint8_t *) buffer; /* XXX this breaks const */"
606+ $as_echo " cycle.tme_bus_cycle_buffer_increment = 1;"
607+ $as_echo " cycle.tme_bus_cycle_lane_routing"
608+ $as_echo " = (bus_device->tme_bus_device_router"
609+ $as_echo " + TME_BUS_ROUTER_INIT_INDEX(TME_BUS${i_width}_LOG2, count, address_init));"
610+ $as_echo ""
611+ $as_echo " /* XXX this should come from a socket configuration: */"
612+ $as_echo " cycle.tme_bus_cycle_port = TME_BUS_CYCLE_PORT(0, TME_BUS${i_width}_LOG2);"
613+ $as_echo ""
614+ $as_echo " /* form the physical address for the bus cycle handler: */"
615+ $as_echo " address_resp = tlb->tme_bus_tlb_addr_offset + address_init;"
616+ $as_echo " shift = tlb->tme_bus_tlb_addr_shift;"
617+ $as_echo " if (shift < 0) {"
618+ $as_echo " address_resp <<= (0 - shift);"
619+ $as_echo " }"
620+ $as_echo " else if (shift > 0) {"
621+ $as_echo " address_resp >>= shift;"
622+ $as_echo " }"
623+ $as_echo " cycle.tme_bus_cycle_address = address_resp;"
624+ $as_echo ""
625+ $as_echo " /* unbusy this TLB entry: */"
626+ $as_echo " tme_bus_tlb_unbusy(tlb);"
627+ $as_echo ""
628+ $as_echo " /* unlock the device: */"
629+ $as_echo " (*bus_device->tme_bus_device_unlock)(bus_device, locks);"
630+ $as_echo ""
631+ $as_echo " /* run the bus cycle: */"
632+ $as_echo " err = (*tlb->tme_bus_tlb_cycle)"
633+ $as_echo " (tlb->tme_bus_tlb_cycle_private, &cycle);"
634+ $as_echo ""
635+ $as_echo " /* if the TLB entry was invalidated before the ${name}: */"
636+ $as_echo " if (err == EBADF"
637+ $as_echo " && tme_bus_tlb_is_invalid(tlb)) {"
638+ $as_echo " count = 0;"
639+ $as_echo " }"
640+ $as_echo ""
641+ $as_echo " /* otherwise, any other error might be a bus error: */"
642+ $as_echo " else if (err != TME_OK) {"
643+ $as_echo " err = tme_bus_tlb_fault(tlb, &cycle, err);"
644+ $as_echo " assert (err != TME_OK);"
645+ $as_echo " }"
646+ $as_echo ""
647+ $as_echo " /* lock the device: */"
648+ $as_echo " (*bus_device->tme_bus_device_lock)(bus_device, locks);"
649+ $as_echo " }"
650+ $as_echo ""
651+ $as_echo " /* update the address, buffer, and size and continue: */"
652+ $as_echo " address_init += count;"
653+ $as_echo " buffer += count;"
654+ $as_echo " size -= count;"
655+ $as_echo " }"
656+ $as_echo ""
657+ $as_echo " return (err);"
658+ $as_echo "}"
659+ done
660+
661+done
662+
663+# done:
664+#
665+exit 0
--- /dev/null
+++ b/generic/fb-xlat-auto.c
@@ -0,0 +1,49709 @@
1+/* automatically generated by fb-xlat-auto.sh, do not edit! */
2+
3+/*
4+ * Copyright (c) 2003, 2005 Matt Fredette
5+ * All rights reserved.
6+ *
7+ * Redistribution and use in source and binary forms, with or without
8+ * modification, are permitted provided that the following conditions
9+ * are met:
10+ * 1. Redistributions of source code must retain the above copyright
11+ * notice, this list of conditions and the following disclaimer.
12+ * 2. Redistributions in binary form must reproduce the above copyright
13+ * notice, this list of conditions and the following disclaimer in the
14+ * documentation and/or other materials provided with the distribution.
15+ * 3. All advertising materials mentioning features or use of this software
16+ * must display the following acknowledgement:
17+ * This product includes software developed by Matt Fredette.
18+ * 4. The name of the author may not be used to endorse or promote products
19+ * derived from this software without specific prior written permission.
20+ *
21+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR
22+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31+ * POSSIBILITY OF SUCH DAMAGE.
32+ */
33+
34+_TME_RCSID("$Id: fb-xlat-auto.sh,v 1.12 2009/08/30 21:51:53 fredette Exp $");
35+
36+/* the central feature of these translation functions is the "bit
37+ FIFO", a first-in, first-out stream of bits. source bit FIFOs are
38+ used to read pixel bits out of source images, and destination bit
39+ FIFOs are used to write pixel bits into destination images.
40+
41+ a bit FIFO has a visible part and an invisible part.
42+
43+ the visible part of a bit FIFO is 32 bits wide, meaning the
44+ translation code can read (for a source bit FIFO) or write (for a
45+ destination bit FIFO) up to 32 bits of pixel data before a bit
46+ FIFO shift.
47+
48+ the invisible part of a source bit FIFO contains pixel bits that
49+ have already been read from the source image memory, but that have
50+ yet to be shifted in to the visible part.
51+
52+ the invisible part of a destination bit FIFO contains the pixel
53+ bits that have been shifted out of the visible part, but that have
54+ yet to be written to the destination image memory.
55+
56+ depending on various attributes of an image format, it may be
57+ possible for the translation code to always read or write the
58+ entire 32 visible bits of a bit FIFO at a time, and as a result
59+ always shift the bit FIFO 32 bits at a time. this is desirable
60+ because it minimizes bit FIFO shifts.
61+
62+ when this does happen, it may also be the case that the visible
63+ part of the bit FIFO always perfectly corresponds to an aligned
64+ 32-bit word in the image buffer.
65+
66+ this is the optimal situation, as it makes it unnecessary to track
67+ the invisible part in C local variables at all - each 32-bit FIFO
68+ shift of a source bit FIFO just reads the next 32-bit word directly
69+ into the visible part, and each 32-bit FIFO shift of a destination
70+ bit FIFO just writes the next 32-bit word directly out of the
71+ visible part.
72+
73+ within the visible part of a bit FIFO, which bits belong to which
74+ pixels depends on the "order" of the image format. most-significant
75+ (big-endian) images have earlier (more to the left on the screen)
76+ pixels in more-significant bit positions. least-significant
77+ (little-endian) images have earlier pixels in less-significant bit
78+ bit positions.
79+
80+ bit significance *within* a pixel never depends on image order.
81+ once the bits belonging to a pixel have been identified according
82+ to image order, the least significant bit in that pixel's value is
83+ always the bit with the least absolute value.
84+
85+ some pictures may help explain this better. each picture shows the
86+ 32 bit visible part of a bit FIFO, with the bits marked from 0
87+ (least significant) to 31 (most significant). all of these
88+ examples are for a two-bit-deep/two-bits-per-pixel image, and in
89+ the visible part sixteen pixels are numbered. lesser numbered
90+ pixels are earlier (more to the left on the screen). some of the
91+ invisible part is also shown, along with the direction that the bit
92+ FIFO shifts in:
93+
94+ a source bit FIFO for a little-endian source image with two bits
95+ per pixel looks like:
96+
97+ |
98+ | 31 30 29 28 7 6 5 4 3 2 1 0
99+ --+--+--+--+--+--+|+--+--+--+--+- --+--+--+--+--+--+--+--+
100+ .. p18 | p17 | p16 ||| p15 | p14 | .. p3 | p2 | p1 | p0 |
101+ --+--+--+--+--+--+|+--+--+--+--+- --+--+--+--+--+--+--+--+
102+ |
103+ invisible part | visible part
104+
105+ shift -> shift -> shift -> shift -> shift ->
106+
107+ a source bit FIFO for a big-endian source image with two bits per
108+ pixel looks like:
109+
110+ |
111+ 31 30 29 28 27 26 25 26 4 3 2 1 0 |
112+ +--+--+--+--+--+--+--+-- -+--+--+--+--+|+--+--+--+--+--+--
113+ | p0 | p1 | p2 | p3 .. | p14 | p15 ||| p16 | p17 | p18 ..
114+ +--+--+--+--+--+--+--+-- -+--+--+--+--+|+--+--+--+--+--+--
115+ |
116+ visible part | invisible part
117+
118+ <- shift <- shift <- shift <- shift <- shift
119+
120+ a destination bit FIFO for a little-endian destination image with
121+ two bits per pixel looks like:
122+
123+ |
124+ 31 30 29 28 27 26 25 26 4 3 2 1 0 |
125+ +--+--+--+--+--+--+--+-- -+--+--+--+--+|+--+--+--+--+--+--
126+ | p23 | p22 | p21 | p20 .. | p9 | p8 ||| p7 | p6 | p5 ..
127+ +--+--+--+--+--+--+--+-- -+--+--+--+--+|+--+--+--+--+--+--
128+ |
129+ visible part | invisible part
130+
131+ shift -> shift -> shift -> shift -> shift ->
132+
133+ a destination bit FIFO for a big-endian destination image with
134+ two bits per pixel looks like:
135+
136+ |
137+ | 31 30 29 28 7 6 5 4 3 2 1 0
138+ --+--+--+--+--+--+|+--+--+--+--+- --+--+--+--+--+--+--+--+
139+ .. p5 | p6 | p7 ||| p8 | p9 | .. p20 | p21 | p22 | p23 |
140+ --+--+--+--+--+--+|+--+--+--+--+- --+--+--+--+--+--+--+--+
141+ |
142+ invisible part | visible part
143+
144+ <- shift <- shift <- shift <- shift <- shift
145+
146+ each translation function has at least one source bit FIFO and at
147+ least one destination bit FIFO. the general idea is to read source
148+ pixel value(s) from the source image, map those source pixel
149+ value(s) somehow into destination pixel value(s), and write those
150+ destination pixel value(s) to the destination image.
151+
152+ translation functions that do not scale the image have exactly one
153+ source bit FIFO and exactly one destination bit FIFO. one pixel
154+ read from the source bit FIFO becomes one pixel written to the
155+ destination bit FIFO.
156+
157+ translation functions that halve the image size have two source bit
158+ FIFOs and one destination bit FIFO. one source bit FIFO sources
159+ bits from an even-numbered scanline, and the other sources bits from
160+ an odd-numbered scanline. four pixels read from the source bit
161+ FIFOs - two from each source bit FIFO, making a 2x2 square - become
162+ one pixel written to the destination bit FIFO.
163+
164+ translation functions that double the image size have one source
165+ bit FIFO and two destination bit FIFOs. one destination bit FIFO
166+ sinks bits for an even-numbered scanline, and the other sinks bits
167+ for an odd-numbered scanline. one pixel read from the source bit
168+ FIFO becomes four pixels written to the destination bit FIFOs -
169+ two to each destination bit FIFO, making a 2x2 square.
170+
171+ translation functions don't necessarily always translate the entire
172+ source image into the entire destination image. instead, the buffer
173+ holding the current source image is expected to be twice as large as
174+ necessary (plus some overhead), with the second half of the buffer
175+ holding a copy of the last translated ("old") source image.
176+
177+ before setting up and translating pixels using bit FIFOs, a
178+ translation function treats the the current and old source images as
179+ an array of aligned 32-bit words and compares them. if it finds no
180+ 32-bit word that has changed, no translation is done and the
181+ function returns.
182+
183+ otherwise, initial source pixel x and y coordinates are derived from
184+ the offset of the 32-bit word that failed comparison, and the source
185+ primary bit FIFO is primed. if this translation function halves the
186+ image size, the source secondary bit FIFO is primed from the same x
187+ coordinate on the "other" (think y ^ 1) scanline.
188+
189+ then, initial destination pixel x and y coordinates are derived from
190+ the initial source x and y coordinates, and the destination primary
191+ bit FIFO is primed. if this translation function doubles the image
192+ size, the destination secondary bit FIFO is primed from the same x
193+ coordinate on the "other" (think y ^ 1) scanline.
194+
195+ as mentioned previously, the buffer holding the current source image
196+ is expected to be twice as large as necessary (plus some overhead),
197+ with the second half of the buffer holding a copy of the last
198+ translated ("old") source image.
199+
200+ this "overhead" is approximately two extra scanlines worth of data,
201+ that is initialized to all-bits-zero and must always remain zero.
202+ this extra data is present at the end of both the current ("new")
203+ and last translated ("old") source images.
204+
205+ these extra, always-blank scanlines guarantee that the pixel
206+ translation loop terminates. the pixel translation loop *never*
207+ checks for the end of the image buffer. instead, it terminates only
208+ after it has read in TME_FB_XLAT_RUN consecutive aligned 32-bit
209+ words that have *not* changed between the new and old source images.
210+ this small amount of extra memory overhead simplifies the pixel
211+ translation loop, because it doesn't have to worry about going past
212+ the end of the actual image.
213+*/
214+
215+
216+/* macros: */
217+
218+/* given a 32-bit aligned pointer into the current source image, this
219+ returns the corresponding 32-bit aligned pointer in the last
220+ translated ("old") source image. since the old source image
221+ follows the current source image, this is simple pointer arithmetic
222+ using src_bypb: */
223+#define TME_FB_XLAT_SRC_OLD(raw) \
224+ ((tme_uint32_t *) (((tme_uint8_t *) (raw)) + src_bypb))
225+
226+/* when the fast, aligned 32-bit word comparison loop finds a word
227+ that has changed in the source image, pixels are translated until
228+ TME_FB_XLAT_RUN consecutive aligned 32-bit words are processed that
229+ have *not* changed in the source image, at which point the fast
230+ comparison loop resumes.
231+
232+ the idea is that after you've started translating pixels, once the
233+ FIFO shift operation has read TME_FB_XLAT_RUN consecutive raw,
234+ unchanged 32-bit words, all of the pixels from previous, changed
235+ 32-bit words have been translated and shifted out of the source bit
236+ FIFO(s), and all bits remaining in the source bit FIFO(s) are for
237+ pixels in those unchanged 32-bit words. since the pixels are
238+ unchanged, pixel translation can stop, and the entire state of the
239+ source bit FIFO(s) can be discarded.
240+
241+ so, each time a raw, changed 32-bit word is read, xlat_run is
242+ reloaded with TME_FB_XLAT_RUN, and each time 32 bits worth of
243+ source image pixels are processed, it is decremented. when it
244+ reaches zero, the source bit FIFO(s) are discarded, the destination
245+ bit FIFO(s) are flushed, the pixel translation loop breaks and the
246+ fast comparison loop continues: */
247+#define TME_FB_XLAT_RUN (2)
248+
249+/* this shifts a source FIFO: */
250+#define TME_FB_XLAT_SHIFT_SRC(unaligned, fifo, next, bits, shift, raw, order)\
251+do { \
252+ \
253+ /* if the source FIFO may not be 32-bit aligned: */ \
254+ if (unaligned) { \
255+ \
256+ /* we must be shifting between 1 and 32 bits: */ \
257+ assert ((shift) >= 1 && (shift) <= 32); \
258+ \
259+ /* the FIFO must have more than 32 bits in it already: */ \
260+ assert (bits > 32); \
261+ \
262+ /* shift the FIFO: */ \
263+ if ((shift) == 32) { \
264+ fifo = next; \
265+ } \
266+ else if (order == TME_ENDIAN_BIG) { \
267+ fifo = (fifo << ((shift) & 31)) | (next >> (32 - (shift)));\
268+ next <<= ((shift) & 31); \
269+ } \
270+ else { \
271+ fifo = (fifo >> ((shift) & 31)) | (next << (32 - (shift)));\
272+ next >>= ((shift) & 31); \
273+ } \
274+ bits -= (shift); \
275+ \
276+ /* if we have a new 32-bit word to read: */ \
277+ if (bits <= 32) { \
278+ next = *raw; \
279+ if (*TME_FB_XLAT_SRC_OLD(raw) != next) { \
280+ *TME_FB_XLAT_SRC_OLD(raw) = next; \
281+ xlat_run = TME_FB_XLAT_RUN; \
282+ } \
283+ raw++; \
284+ next = (order == TME_ENDIAN_BIG \
285+ ? tme_betoh_u32(next) \
286+ : tme_letoh_u32(next)); \
287+ \
288+ /* before the load, if there were fewer than 32 bits \
289+ remaining in the FIFO, shift bits from the word \
290+ we just loaded into their proper positions: */ \
291+ if (bits < 32) { \
292+ if (order == TME_ENDIAN_BIG) { \
293+ fifo |= (next >> bits); \
294+ next <<= (32 - bits); \
295+ } \
296+ else { \
297+ fifo |= (next << bits); \
298+ next >>= (32 - bits); \
299+ } \
300+ } \
301+ \
302+ /* there are now 32 more bits in the FIFO: */ \
303+ bits += 32; \
304+ } \
305+ } \
306+ \
307+ /* otherwise, if the source FIFO is always 32-bit aligned: */ \
308+ else { \
309+ \
310+ /* we must be shifting exactly 32 bits: */ \
311+ assert((shift) == 32); \
312+ \
313+ /* load the next 32-bit word: */ \
314+ fifo = *raw; \
315+ if (*TME_FB_XLAT_SRC_OLD(raw) != fifo) { \
316+ *TME_FB_XLAT_SRC_OLD(raw) = fifo; \
317+ xlat_run = TME_FB_XLAT_RUN; \
318+ } \
319+ raw++; \
320+ fifo = (order == TME_ENDIAN_BIG \
321+ ? tme_betoh_u32(fifo) \
322+ : tme_letoh_u32(fifo)); \
323+ } \
324+} while (/* CONSTCOND */ 0)
325+
326+/* this shifts a destination FIFO: */
327+#define TME_FB_XLAT_SHIFT_DST(unaligned, fifo, next, bits, shift, raw, order)\
328+do { \
329+ \
330+ /* if the destination FIFO may not be 32-bit aligned: */ \
331+ if (unaligned) { \
332+ \
333+ /* we must be shifting between 1 and 32 bits: */ \
334+ assert ((shift) >= 1 && (shift) <= 32); \
335+ \
336+ /* the FIFO must have fewer than 32 bits in it: */ \
337+ assert (bits < 32); \
338+ \
339+ /* shift the FIFO: */ \
340+ if (order == TME_ENDIAN_BIG) { \
341+ next |= (fifo >> bits); \
342+ fifo <<= (32 - bits); \
343+ } \
344+ else { \
345+ next |= (fifo << bits); \
346+ fifo >>= (32 - bits); \
347+ } \
348+ if (SHIFTMAX_INT32_T < 32 && bits == 0) { \
349+ fifo = 0; \
350+ } \
351+ bits += (shift); \
352+ \
353+ /* if we have a completed 32-bit word to write: */ \
354+ if (bits >= 32) { \
355+ *(raw++) = (order == TME_ENDIAN_BIG \
356+ ? tme_htobe_u32(next) \
357+ : tme_htole_u32(next)); \
358+ bits -= 32; \
359+ assert(bits != 0 || fifo == 0); \
360+ next = fifo; \
361+ } \
362+ } \
363+ \
364+ /* the destination FIFO is always 32-bit aligned: */ \
365+ else { \
366+ \
367+ /* we must be shifting exactly 32 bits: */ \
368+ assert((shift) == 32); \
369+ \
370+ /* store the next 32-bit word: */ \
371+ *(raw++) = (order == TME_ENDIAN_BIG \
372+ ? tme_htobe_u32(fifo) \
373+ : tme_htole_u32(fifo)); \
374+ \
375+ } \
376+ \
377+ /* clear the writable part of the FIFO: */ \
378+ fifo = 0; \
379+} while (/* CONSTCOND */ 0)
380+
381+/* _TME_FB_XLAT_MAP_LINEAR_SCALE gives the factor needed to scale a
382+ masked value up or down to a given size in bits. for example, if a
383+ value's mask is 0xf800 (a five bit mask), and the value needs to be
384+ scaled up to seven bits, this gives an factor of four. if a
385+ value's mask is 0x7e0 (a six bit mask), and the value needs to be
386+ scaled down to three bits, this gives a factor of eight: */
387+#define _TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out) \
388+ (TME_FB_XLAT_MAP_BASE_MASK(mask_in) \
389+ ^ TME_FB_XLAT_MAP_BASE_MASK(mask_out))
390+#define TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out) \
391+ (_TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out) \
392+ ? (TME_FB_XLAT_MAP_BASE_MASK(_TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out))\
393+ + 1) \
394+ : 1)
395+
396+/* this linearly maps a value from one mask to another: */
397+#define _TME_FB_XLAT_MAP_LINEAR(value, mask_in, mask_out) \
398+ \
399+ /* if the value does not need to be scaled up: */ \
400+ (((TME_FB_XLAT_MAP_BASE_MASK(mask_out) \
401+ <= TME_FB_XLAT_MAP_BASE_MASK(mask_in)) \
402+ ? \
403+ \
404+ /* extract the value and scale it down: */ \
405+ (TME_FIELD_MASK_EXTRACTU(value, mask_in) \
406+ / TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out)) \
407+ \
408+ /* otherwise, the value needs to be scaled up: */ \
409+ : \
410+ \
411+ /* extract the value: */ \
412+ ((TME_FIELD_MASK_EXTRACTU(value, mask_in) \
413+ \
414+ /* scale it up: */ \
415+ * TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out)) \
416+ \
417+ /* if the least significant bit of the value is set, add \
418+ in the scale minus one. this makes the linear mapping \
419+ at least cover the entire range: */ \
420+ + (((value / \
421+ _TME_FIELD_MASK_FACTOR(mask_in)) \
422+ & 1) \
423+ * (TME_FB_XLAT_MAP_LINEAR_SCALE(mask_in, mask_out) \
424+ - 1)))) \
425+ \
426+ /* finally, shift the value into position: */ \
427+ * _TME_FIELD_MASK_FACTOR(mask_out))
428+
429+/* this indexes a value: */
430+#define _TME_FB_XLAT_MAP_INDEX(value, mask_out, index) \
431+ \
432+ /* intensities are either stored as 8 or 16 bits: */ \
433+ (((TME_FB_XLAT_MAP_BASE_MASK(mask_out) <= 0xff) \
434+ ? ((const tme_uint8_t *) (index))[(value)] \
435+ : ((const tme_uint16_t *) (index))[(value)]) \
436+ \
437+ /* shift the value into position: */ \
438+ * _TME_FIELD_MASK_FACTOR(mask_out))
439+
440+/* this maps one subfield or intensity value into another subfield or
441+ intensity value: */
442+#define TME_FB_XLAT_MAP(value, mask_in, mask_out, indexed, index)\
443+ \
444+ /* do the linear mapping or the index mapping: */ \
445+ ((!(indexed)) \
446+ ? _TME_FB_XLAT_MAP_LINEAR(value, mask_in, mask_out) \
447+ : _TME_FB_XLAT_MAP_INDEX(TME_FIELD_MASK_EXTRACTU(value, mask_in), mask_out, index))
448+
449+/* this translates frame buffer contents from this source format:
450+ 1152x900
451+ 1 bit deep, 1 bit per pixel, 0 pixels skipped, 32-bit scanline padding, MSB-first, color, index mapped pixels, 8 bits per mapped intensity, no g mask, no r mask, no b mask
452+ to this destination format:
453+ 24 bits deep, 32 bits per pixel, 0 pixels skipped, 32-bit scanline padding, LSB-first, linearly mapped pixels, a g mask of 0xff00, a r mask of 0xff0000, a b mask of 0xff
454+*/
455+static int
456+tme_fb_xlat0(struct tme_fb_connection *src,
457+ struct tme_fb_connection *dst)
458+{
459+
460+ /* whenever possible we define macros instead of declaring
461+ variables, for optimization: */
462+
463+ /* declare src_x and src_y. these are the current translation
464+ coordinates in the source image: */
465+ unsigned int src_x, src_y;
466+
467+ /* declare dst_x and dst_y. these are the current translation
468+ coordinates in the destination image. since this function
469+ does not scale the image, these coordinates are always
470+ the same as the coordinates in the source image: */
471+#define dst_x (src_x)
472+#define dst_y (src_y)
473+
474+ /* declare pixel. this holds a single pixel value being translated
475+ for the destination image: */
476+ tme_uint32_t pixel;
477+
478+ /* declare src_width and dst_width. these are in terms of pixels: */
479+#define src_width (1152)
480+#define dst_width (src_width)
481+
482+ /* declare src_depth, the source pixel depth, which is in
483+ terms of bits. declare src_mask, which is the corresponding
484+ mask of one bits: */
485+#define src_depth (1)
486+#define src_mask (0xffffffff >> (32 - src_depth))
487+
488+ /* declare src_bipp and dst_bipp. these are the bits-per-pixel
489+ values for the source and destination images: */
490+#define src_bipp (1)
491+#define dst_bipp (32)
492+
493+ /* declare src_skipx and dst_skipx. these are the counts of
494+ undisplayed pixels at the beginning of each scanline in the
495+ source and destination images: */
496+#define src_skipx (0)
497+#define dst_skipx (0)
498+
499+ /* declare src_pad and dst_pad. these are the paddings, in bits,
500+ of each scanline in the source and destination images: */
501+#define src_pad (32)
502+#define dst_pad (32)
503+
504+ /* declare src_order and dst_order. these are the bit and byte
505+ orders (either TME_ENDIAN_BIG or TME_ENDIAN_LITTLE) of the
506+ source and destination images. since these values profoundly
507+ affect optimization, they are always constant: */
508+#define src_order (TME_ENDIAN_BIG)
509+#define dst_order (TME_ENDIAN_LITTLE)
510+
511+ /* declare src_bypl and dst_bypl. these are the bytes per scanline
512+ in the source and destination images. these values are calculated
513+ from the count of undisplayed and displayed pixels per scanline,
514+ the number of bits per pixel, and the scanline padding: */
515+#define src_bypl (((((src_skipx + src_width) * src_bipp) + (src_pad - 1)) & -src_pad) / 8)
516+#define dst_bypl (((((dst_skipx + dst_width) * dst_bipp) + (dst_pad - 1)) & -dst_pad) / 8)
517+
518+ /* declare src_packed and dst_packed. these are nonzero iff
519+ every last bit in a scanline belongs to a displayed pixel.
520+ put another way, this is zero iff a scanline has undisplayed
521+ pixels at its beginning or padding bits at its end. when
522+ a source image or destination image is packed, translation
523+ doesn't have to worry about skipping FIFO bits to get to
524+ bits belonging to displayed pixels: */
525+#define src_packed ((src_width * src_bipp) == (src_bypl * 8))
526+#define dst_packed ((dst_width * dst_bipp) == (dst_bypl * 8))
527+
528+ /* declare src_bypb and src_bypb_real. src_bypb is the bytes
529+ per source image buffer with the "translation termination
530+ overhead" of approximately two extra scanlines. src_bypb_real
531+ is the real bytes per source image buffer with no overhead.
532+ both values are padded to a multiple of 4 bytes (32 bits): */
533+#define src_bypb_real (((900 * src_bypl) + 3) & -4)
534+#define src_bypb ((src_bypb_real + (src_bypl * 2)) & -4)
535+
536+ /* declare the source primary bit FIFO:
537+
538+ src_raw0 points to the next aligned 32-bit word to be
539+ read from the image buffer.
540+
541+ src_fifo0 is the visible part of the bit FIFO.
542+
543+ src_fifo0_next and src_fifo0_bits are only used when the
544+ visible part of the bit FIFO is not guaranteed to always
545+ correspond to an aligned 32-bit word in the image buffer.
546+ src_fifo0_next is the invisible part of the bit FIFO,
547+ and src_fifo0_bits tracks the total number of bits in the
548+ visible and invisible parts of the FIFO. */
549+ const tme_uint32_t *src_raw0;
550+ tme_uint32_t src_fifo0, src_fifo0_next;
551+ unsigned int src_fifo0_bits;
552+
553+ /* declare the destination primary bit FIFO:
554+
555+ dst_raw0 points to the next aligned 32-bit word to be
556+ written into the image buffer.
557+
558+ dst_fifo0 is the visible part of the bit FIFO.
559+
560+ dst_fifo0_next and dst_fifo0_bits are only used when the
561+ visible part of the bit FIFO is not guaranteed to always
562+ correspond to an aligned 32-bit word in the image buffer.
563+ dst_fifo0_next is the invisible part of the bit FIFO,
564+ and dst_fifo0_bits tracks the total number of bits in the
565+ invisible part of the FIFO. */
566+ tme_uint32_t *dst_raw0;
567+ tme_uint32_t dst_fifo0, dst_fifo0_next;
568+ unsigned int dst_fifo0_bits;
569+
570+ /* declare src_off and dst_off. these are used when priming a
571+ source or destination bit FIFO, to identify an initial aligned
572+ 32-bit word in the source or destination image buffer, and an
573+ initial bit offset within that word: */
574+ unsigned int src_off, dst_off;
575+
576+ /* declare src_fifo0_may_be_unaligned. this is zero iff all
577+ aligned 32-bit words in the source buffer contain a whole
578+ number of displayed pixels, and at *all times during the
579+ translation* the visible part of the bit FIFO is guaranteed
580+ to correspond to an aligned 32-bit word in the image buffer.
581+
582+ this is *not* so if any of the following are true:
583+
584+ - the source bits-per-pixel value is not known at compile
585+ time. in this case, we can't unroll the translation loop
586+ for source pixels, and are forced to shift the FIFO after
587+ each one.
588+
589+ - if the source image is not packed. in this case, there may
590+ be undisplayed pixels in the FIFO, which we will need to
591+ shift out.
592+
593+ - if there are 24 bits per source pixel. in this case, a
594+ source pixel may cross a 32-bit boundary: */
595+#define src_fifo0_may_be_unaligned (!src_packed || (src_bipp == 24))
596+
597+ /* declare dst_fifo0_may_be_unaligned. this is zero iff all
598+ aligned 32-bit words in the destination buffer contain a whole
599+ number of displayed pixels, and at *all times during the
600+ translation* the visible part of the bit FIFO is guaranteed
601+ to correspond to an aligned 32-bit word in the image buffer.
602+
603+ this is *not* so if any of the following are true:
604+
605+ - the destination bits-per-pixel value is not known at compile
606+ time. in this case, we can't unroll the translation loop
607+ for destination pixels, and are forced to shift the FIFO
608+ after each one.
609+
610+ - if src_fifo0_may_be_unaligned is true. in this case, we
611+ definitely can't guarantee that any initial dst_x will
612+ correspond to an aligned 32-bit word in the destination buffer.
613+
614+ - if the destination image is not packed. in this case, there may
615+ be undisplayed pixels in the FIFO, which we will need to
616+ shift out.
617+
618+ - if there are 24 bits per destination pixel. in this case,
619+ a destination pixel may cross a 32-bit boundary.
620+
621+ - if a possible initial dst_x doesn't correspond to an aligned
622+ 32-bit word in the destination buffer. for this last one:
623+
624+ since we require that src_fifo0_may_be_unaligned is zero, we
625+ know that the initial src_x = (Z * 32) / src_bipp for
626+ some Z. we also have the initial dst_x = src_x.
627+ the initial destination bit offset will then be:
628+
629+ (dst_skipx + dst_x) * dst_bipp
630+ = (dst_skipx * dst_bipp) + (dst_x * dst_bipp)
631+
632+ if we additionally require that (dst_skipx * dst_bipp)
633+ be 32-bit aligned, this reduces things to:
634+
635+ dst_x * dst_bipp
636+ = (src_x) * dst_bipp
637+ = (((Z * 32) / src_bipp)) * dst_bipp
638+
639+ which will be a multiple of 32 iff:
640+
641+ ((1 / src_bipp)) * dst_bipp >= 1 and integral
642+
643+ or, equivalently:
644+
645+ (dst_bipp % src_bipp) == 0
646+ */
647+#define dst_fifo0_may_be_unaligned (src_fifo0_may_be_unaligned || !dst_packed || (dst_bipp == 24) || (dst_bypl % 4) || ((dst_skipx * dst_bipp) % 32) || (dst_bipp % src_bipp))
648+
649+ /* declare src_offset_updated_first and src_offset_updated_last,
650+ which hold the offsets of the first and last updated bytes in
651+ the source image: */
652+ tme_uint32_t src_offset_updated_first;
653+ tme_uint32_t src_offset_updated_last;
654+
655+ /* declare src_raw0_end. when treating the source image as
656+ an array of aligned 32-bit words, this variable holds the
657+ address of the first word after the real source image.
658+ if the fast, aligned 32-bit word comparison loop passes
659+ this point, the entire source image has been processed and
660+ the function terminates: */
661+ const tme_uint32_t *src_raw0_end;
662+
663+ /* declare xlat_run. see the comment for the TME_FB_XLAT_RUN
664+ macro for an explanation of what this variable does: */
665+ int xlat_run;
666+
667+ /* this silences gcc -Wuninitialized: */
668+ src_fifo0_next = 0;
669+ src_fifo0_bits = 0;
670+ dst_fifo0_next = 0;
671+ dst_fifo0_bits = 0;
672+
673+ /* initialize src_raw0 and src_raw0_end for the fast aligned 32-bit
674+ word comparison loop. on entry to (and when continuing) that loop,
675+ src_raw0 always points to the aligned 32-bit word *before* the
676+ next word to check. src_raw0_end always points after the last
677+ word to check.
678+
679+ src_raw0 is actually part of the source primary bit FIFO, which
680+ is good, because when the fast comparison fails on a word, src_raw0
681+ is already primed and ready to work for that bit FIFO: */
682+ src_offset_updated_first = src->tme_fb_connection_offset_updated_first;
683+ src_offset_updated_last = TME_MIN(src->tme_fb_connection_offset_updated_last, src_bypb_real - 1);
684+ src->tme_fb_connection_offset_updated_first = 0;
685+ src->tme_fb_connection_offset_updated_last = src_bypb_real - 1;
686+ if (src_offset_updated_first > src_offset_updated_last) {
687+ return (FALSE);
688+ }
689+ src_raw0
690+ = (((const tme_uint32_t *)
691+ (src->tme_fb_connection_buffer
692+ + (src_offset_updated_first
693+ & (0 - (tme_uint32_t) sizeof(tme_uint32_t)))))
694+ -1);
695+ src_raw0_end
696+ = ((const tme_uint32_t *)
697+ (src->tme_fb_connection_buffer
698+ + src_offset_updated_last
699+ + 1));
700+
701+ /* initialize xlat_run to -1. it can never go negative inside the
702+ pixel translation loop, so if xlat_run stays negative for the
703+ entire translation, it means that the source image hasn't changed
704+ since the last translation. this information is returned to the
705+ caller to hopefully save more work in updating the display: */
706+ xlat_run = -1;
707+
708+ /* this is the main translation loop, which contains the fast aligned
709+ 32-bit word comparison loop, and the pixel translation loop: */
710+ for (;;) {
711+
712+ /* this is the fast aligned 32-bit word comparison loop. it
713+ terminates either when a word fails comparison, or when the
714+ entire source image has been compared. the if test that
715+ follows checks for the latter case and breaks the main
716+ translation loop: */
717+ for (; (++src_raw0 < src_raw0_end
718+ && *src_raw0 == *TME_FB_XLAT_SRC_OLD(src_raw0)); );
719+ if (src_raw0 >= src_raw0_end) {
720+ break;
721+ }
722+
723+ /* calculate the byte offset into the source buffer of the
724+ 32-bit word that failed comparison: */
725+ src_off = ((tme_uint8_t *) src_raw0) - src->tme_fb_connection_buffer;
726+
727+ /* calculate the source y pixel coordinate, and reduce
728+ src_off from the byte offset into the buffer to the
729+ byte offset into that scanline: */
730+ src_y = src_off / src_bypl;
731+ src_off = src_off % src_bypl;
732+
733+ /* while translating pixels, we use one or more "bit FIFOs",
734+ each composed of one or more 32-bit integers. we load these
735+ FIFOs 32 bits at a time. */
736+
737+ /* prime the visible part of the source primary bit FIFO: */
738+ src_fifo0 = *src_raw0;
739+ *TME_FB_XLAT_SRC_OLD(src_raw0) = src_fifo0;
740+ src_raw0++;
741+ src_fifo0 = ((src_order == TME_ENDIAN_BIG)
742+ ? tme_betoh_u32(src_fifo0)
743+ : tme_letoh_u32(src_fifo0));
744+
745+ /* if the source primary bit FIFO may be unaligned: */
746+ if (src_fifo0_may_be_unaligned) {
747+
748+ /* prime the invisible part of the source primary bit FIFO and
749+ assume that we will not have to shift it to finish: */
750+ src_fifo0_next = *src_raw0;
751+ *TME_FB_XLAT_SRC_OLD(src_raw0) = src_fifo0_next;
752+ src_raw0++;
753+ src_fifo0_next = ((src_order == TME_ENDIAN_BIG)
754+ ? tme_betoh_u32(src_fifo0_next)
755+ : tme_letoh_u32(src_fifo0_next));
756+ src_fifo0_bits = 0;
757+
758+ /* if there are pixels that need to be skipped, the first 32 bits
759+ we loaded into the FIFO may have first bits that belong to
760+ those undisplayed (skipped) pixels. it is *not* possible for
761+ it to have first bits that belong to the scanline pad; there
762+ might be pad bits in the *middle* of the first 32 bits, but any
763+ first bits *must* belong to pixels, displayed or not: */
764+ if (src_skipx > 0
765+ && (src_off * 8) < (src_skipx * src_bipp)) {
766+
767+ /* see how many bits we will need to skip: */
768+ src_fifo0_bits = (src_skipx * src_bipp) - (src_off * 8);
769+
770+ /* if it is more than 31 bits, this is an entire 32 bits of
771+ undisplayed pixels. just advance: */
772+ if (src_fifo0_bits > 31) {
773+ src_raw0--;
774+ continue;
775+ }
776+
777+ /* set the source x coordinate to zero: */
778+ src_x = 0;
779+ }
780+
781+ /* otherwise, the first 32 bits we load will have first bits for
782+ a displayable pixel: */
783+ else {
784+
785+ /* if the source bits per pixel is 24, calculate the number of
786+ bytes *before* the original src_raw0 of any split pixel, and
787+ subtract this from src_off, to leave src_off as the byte offset
788+ into the scanline of the beginning of a pixel: */
789+ if (src_bipp == 24) {
790+ src_fifo0_bits = (src_off % 3);
791+ src_off -= src_fifo0_bits;
792+
793+ /* if this is a split pixel, we need to prime the source primary
794+ bit FIFO starting with the part *before* the original src_raw0.
795+ we do not have to copy to the old; it passed comparison: */
796+ if (src_fifo0_bits) {
797+ src_raw0--;
798+ src_fifo0_next = src_fifo0;
799+ src_fifo0 = ((src_order == TME_ENDIAN_BIG)
800+ ? tme_betoh_u32(*(src_raw0 - 2))
801+ : tme_letoh_u32(*(src_raw0 - 2)));
802+ }
803+ }
804+
805+ /* calculate the source x coordinate: */
806+ src_x = ((src_off * 8) / src_bipp) - src_skipx;
807+ }
808+
809+ /* do any shifting to finish priming the source primary FIFO: */
810+ if (src_fifo0_bits) {
811+ if (src_order == TME_ENDIAN_BIG) {
812+ src_fifo0 = (src_fifo0 << src_fifo0_bits) | (src_fifo0_next >> (32 - src_fifo0_bits));
813+ src_fifo0_next <<= src_fifo0_bits;
814+ }
815+ else {
816+ src_fifo0 = (src_fifo0 >> src_fifo0_bits) | (src_fifo0_next << (32 - src_fifo0_bits));
817+ src_fifo0_next >>= src_fifo0_bits;
818+ }
819+ }
820+ src_fifo0_bits = 64 - src_fifo0_bits;
821+ }
822+
823+ /* otherwise, the source primary FIFO is aligned: */
824+ else {
825+ src_x = ((src_off * 8) / src_bipp) - src_skipx;
826+ }
827+
828+ /* prime the destination primary bit FIFO: */
829+ dst_fifo0 = 0;
830+ if (dst_fifo0_may_be_unaligned) {
831+
832+ /* calculate the bit offset into the destination buffer of
833+ the destination pixel: */
834+ dst_off = (dst_y * dst_bypl * 8) + ((dst_skipx + dst_x) * dst_bipp);
835+
836+ /* calculate the number of bits that will be in the primed FIFO: */
837+ dst_fifo0_bits = dst_off % 32;
838+
839+ /* set dst_raw0: */
840+ dst_raw0 = (tme_uint32_t *)
841+ (dst->tme_fb_connection_buffer
842+ + ((dst_off - dst_fifo0_bits) / 8));
843+
844+ /* prime the primary destination FIFO: */
845+ dst_fifo0_next = 0;
846+ if (dst_fifo0_bits) {
847+ dst_fifo0_next = (src_order == TME_ENDIAN_BIG
848+ ? (tme_betoh_u32(*dst_raw0) & (0xffffffffUL << (32 - dst_fifo0_bits)))
849+ : (tme_letoh_u32(*dst_raw0) & (0xffffffffUL >> (32 - dst_fifo0_bits))));
850+ }
851+ }
852+
853+ /* otherwise the destination primary FIFO is aligned: */
854+ else {
855+ dst_off = (dst_y * dst_bypl) + (((dst_skipx + dst_x) * dst_bipp) / 8);
856+ dst_raw0 = (tme_uint32_t *) (dst->tme_fb_connection_buffer + dst_off);
857+ }
858+
859+ /* since src_bipp is known at code-generation time, the
860+ pixel translation loop is unrolled to translate all
861+ source pixels in the 32-bit visible part of the source
862+ bit FIFO(s) before shifting.
863+
864+ in this case, src_bipp is known to be 1, so 32 pixels will
865+ be read out of the source bit FIFO(s) before shifting, and
866+ when the source bit FIFO(s) are shifted, they are shifted
867+ 32 bits at a time: */
868+
869+ /* since dst_bipp is known at code-generation time, the pixel
870+ translation loop is unrolled to translate all destination
871+ pixels in the 32-bit visible part of the destination bit
872+ FIFO(s) before shifting.
873+
874+ in this case, dst_bipp is known to be 32, so 1 pixels will
875+ be written into the destination bit FIFO(s) before shifting,
876+ and when the destination bit FIFO(s) are shifted, they are
877+ shifted 32 bits at a time: */
878+
879+ /* src_unroll = 32, src_iter_scale = 1
880+ dst_unroll = 1, dst_iter_scale = 1 */
881+ for (xlat_run = TME_FB_XLAT_RUN;
882+ xlat_run > 0; ) {
883+
884+ /* iter #0 */
885+
886+ /* get a pixel from the source primary FIFO: */
887+ pixel =
888+ ((src_fifo0
889+ >> (src_order == TME_ENDIAN_BIG
890+ ? (32 - (src_bipp + (0 * src_bipp)))
891+ : (0 * src_bipp))));
892+
893+ /* since source pixels are known at compile time to
894+ not have subfields, map the source pixel into the
895+ destination pixel: */
896+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
897+
898+ /* if the source buffer is not packed, and we just
899+ read the last pixel on this source scanline: */
900+ if (!src_packed
901+ && ++src_x == src_width) {
902+
903+ /* calculate the number of bits between the
904+ last bit of the last pixel and the first bit
905+ of the first displayed pixel on the next
906+ scanline. this is equal to the number of
907+ pad bits plus bits for undisplayed pixels: */
908+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
909+
910+ /* while there are bits to shift: */
911+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
912+
913+ /* shift the source primary FIFO: */
914+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
915+ src_fifo0,
916+ src_fifo0_next,
917+ src_fifo0_bits,
918+ TME_MIN(src_off, 32),
919+ src_raw0,
920+ src_order);
921+ }
922+
923+ /* we are now on the first pixel of the next scanline: */
924+ src_x = 0;
925+ }
926+
927+ /* put the pixel into the destination primary FIFO: */
928+ dst_fifo0 |=
929+ (pixel
930+ << (dst_order == TME_ENDIAN_BIG
931+ ? ((32 - dst_bipp) - (0 * dst_bipp))
932+ : (0 * dst_bipp)));
933+
934+ /* if the destination buffer is not packed, and we just
935+ wrote the last pixel on this destination scanline: */
936+ if (!dst_packed
937+ && (dst_x += 1) == dst_width) {
938+
939+ /* calculate the number of bits between the
940+ last bit of the last pixel and the first bit
941+ of the first displayed pixel on the next
942+ scanline. this is equal to the number of
943+ pad bits plus bits for undisplayed pixels: */
944+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
945+
946+ /* while there are bits to shift: */
947+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
948+
949+ /* shift the destination primary FIFO: */
950+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
951+ dst_fifo0,
952+ dst_fifo0_next,
953+ dst_fifo0_bits,
954+ TME_MIN(dst_off, 32),
955+ dst_raw0,
956+ dst_order);
957+ }
958+
959+ /* we are now on the first pixel of the next scanline: */
960+ dst_x = 0;
961+ }
962+
963+ /* shift the destination primary FIFO: */
964+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
965+ dst_fifo0,
966+ dst_fifo0_next,
967+ dst_fifo0_bits,
968+ 32,
969+ dst_raw0,
970+ dst_order);
971+
972+ /* iter #1 */
973+
974+ /* get a pixel from the source primary FIFO: */
975+ pixel =
976+ ((src_fifo0
977+ >> (src_order == TME_ENDIAN_BIG
978+ ? (32 - (src_bipp + (1 * src_bipp)))
979+ : (1 * src_bipp))));
980+
981+ /* since source pixels are known at compile time to
982+ not have subfields, map the source pixel into the
983+ destination pixel: */
984+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
985+
986+ /* if the source buffer is not packed, and we just
987+ read the last pixel on this source scanline: */
988+ if (!src_packed
989+ && ++src_x == src_width) {
990+
991+ /* calculate the number of bits between the
992+ last bit of the last pixel and the first bit
993+ of the first displayed pixel on the next
994+ scanline. this is equal to the number of
995+ pad bits plus bits for undisplayed pixels: */
996+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
997+
998+ /* while there are bits to shift: */
999+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1000+
1001+ /* shift the source primary FIFO: */
1002+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1003+ src_fifo0,
1004+ src_fifo0_next,
1005+ src_fifo0_bits,
1006+ TME_MIN(src_off, 32),
1007+ src_raw0,
1008+ src_order);
1009+ }
1010+
1011+ /* we are now on the first pixel of the next scanline: */
1012+ src_x = 0;
1013+ }
1014+
1015+ /* put the pixel into the destination primary FIFO: */
1016+ dst_fifo0 |=
1017+ (pixel
1018+ << (dst_order == TME_ENDIAN_BIG
1019+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1020+ : (0 * dst_bipp)));
1021+
1022+ /* if the destination buffer is not packed, and we just
1023+ wrote the last pixel on this destination scanline: */
1024+ if (!dst_packed
1025+ && (dst_x += 1) == dst_width) {
1026+
1027+ /* calculate the number of bits between the
1028+ last bit of the last pixel and the first bit
1029+ of the first displayed pixel on the next
1030+ scanline. this is equal to the number of
1031+ pad bits plus bits for undisplayed pixels: */
1032+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1033+
1034+ /* while there are bits to shift: */
1035+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1036+
1037+ /* shift the destination primary FIFO: */
1038+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1039+ dst_fifo0,
1040+ dst_fifo0_next,
1041+ dst_fifo0_bits,
1042+ TME_MIN(dst_off, 32),
1043+ dst_raw0,
1044+ dst_order);
1045+ }
1046+
1047+ /* we are now on the first pixel of the next scanline: */
1048+ dst_x = 0;
1049+ }
1050+
1051+ /* shift the destination primary FIFO: */
1052+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1053+ dst_fifo0,
1054+ dst_fifo0_next,
1055+ dst_fifo0_bits,
1056+ 32,
1057+ dst_raw0,
1058+ dst_order);
1059+
1060+ /* iter #2 */
1061+
1062+ /* get a pixel from the source primary FIFO: */
1063+ pixel =
1064+ ((src_fifo0
1065+ >> (src_order == TME_ENDIAN_BIG
1066+ ? (32 - (src_bipp + (2 * src_bipp)))
1067+ : (2 * src_bipp))));
1068+
1069+ /* since source pixels are known at compile time to
1070+ not have subfields, map the source pixel into the
1071+ destination pixel: */
1072+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1073+
1074+ /* if the source buffer is not packed, and we just
1075+ read the last pixel on this source scanline: */
1076+ if (!src_packed
1077+ && ++src_x == src_width) {
1078+
1079+ /* calculate the number of bits between the
1080+ last bit of the last pixel and the first bit
1081+ of the first displayed pixel on the next
1082+ scanline. this is equal to the number of
1083+ pad bits plus bits for undisplayed pixels: */
1084+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1085+
1086+ /* while there are bits to shift: */
1087+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1088+
1089+ /* shift the source primary FIFO: */
1090+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1091+ src_fifo0,
1092+ src_fifo0_next,
1093+ src_fifo0_bits,
1094+ TME_MIN(src_off, 32),
1095+ src_raw0,
1096+ src_order);
1097+ }
1098+
1099+ /* we are now on the first pixel of the next scanline: */
1100+ src_x = 0;
1101+ }
1102+
1103+ /* put the pixel into the destination primary FIFO: */
1104+ dst_fifo0 |=
1105+ (pixel
1106+ << (dst_order == TME_ENDIAN_BIG
1107+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1108+ : (0 * dst_bipp)));
1109+
1110+ /* if the destination buffer is not packed, and we just
1111+ wrote the last pixel on this destination scanline: */
1112+ if (!dst_packed
1113+ && (dst_x += 1) == dst_width) {
1114+
1115+ /* calculate the number of bits between the
1116+ last bit of the last pixel and the first bit
1117+ of the first displayed pixel on the next
1118+ scanline. this is equal to the number of
1119+ pad bits plus bits for undisplayed pixels: */
1120+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1121+
1122+ /* while there are bits to shift: */
1123+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1124+
1125+ /* shift the destination primary FIFO: */
1126+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1127+ dst_fifo0,
1128+ dst_fifo0_next,
1129+ dst_fifo0_bits,
1130+ TME_MIN(dst_off, 32),
1131+ dst_raw0,
1132+ dst_order);
1133+ }
1134+
1135+ /* we are now on the first pixel of the next scanline: */
1136+ dst_x = 0;
1137+ }
1138+
1139+ /* shift the destination primary FIFO: */
1140+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1141+ dst_fifo0,
1142+ dst_fifo0_next,
1143+ dst_fifo0_bits,
1144+ 32,
1145+ dst_raw0,
1146+ dst_order);
1147+
1148+ /* iter #3 */
1149+
1150+ /* get a pixel from the source primary FIFO: */
1151+ pixel =
1152+ ((src_fifo0
1153+ >> (src_order == TME_ENDIAN_BIG
1154+ ? (32 - (src_bipp + (3 * src_bipp)))
1155+ : (3 * src_bipp))));
1156+
1157+ /* since source pixels are known at compile time to
1158+ not have subfields, map the source pixel into the
1159+ destination pixel: */
1160+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1161+
1162+ /* if the source buffer is not packed, and we just
1163+ read the last pixel on this source scanline: */
1164+ if (!src_packed
1165+ && ++src_x == src_width) {
1166+
1167+ /* calculate the number of bits between the
1168+ last bit of the last pixel and the first bit
1169+ of the first displayed pixel on the next
1170+ scanline. this is equal to the number of
1171+ pad bits plus bits for undisplayed pixels: */
1172+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1173+
1174+ /* while there are bits to shift: */
1175+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1176+
1177+ /* shift the source primary FIFO: */
1178+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1179+ src_fifo0,
1180+ src_fifo0_next,
1181+ src_fifo0_bits,
1182+ TME_MIN(src_off, 32),
1183+ src_raw0,
1184+ src_order);
1185+ }
1186+
1187+ /* we are now on the first pixel of the next scanline: */
1188+ src_x = 0;
1189+ }
1190+
1191+ /* put the pixel into the destination primary FIFO: */
1192+ dst_fifo0 |=
1193+ (pixel
1194+ << (dst_order == TME_ENDIAN_BIG
1195+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1196+ : (0 * dst_bipp)));
1197+
1198+ /* if the destination buffer is not packed, and we just
1199+ wrote the last pixel on this destination scanline: */
1200+ if (!dst_packed
1201+ && (dst_x += 1) == dst_width) {
1202+
1203+ /* calculate the number of bits between the
1204+ last bit of the last pixel and the first bit
1205+ of the first displayed pixel on the next
1206+ scanline. this is equal to the number of
1207+ pad bits plus bits for undisplayed pixels: */
1208+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1209+
1210+ /* while there are bits to shift: */
1211+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1212+
1213+ /* shift the destination primary FIFO: */
1214+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1215+ dst_fifo0,
1216+ dst_fifo0_next,
1217+ dst_fifo0_bits,
1218+ TME_MIN(dst_off, 32),
1219+ dst_raw0,
1220+ dst_order);
1221+ }
1222+
1223+ /* we are now on the first pixel of the next scanline: */
1224+ dst_x = 0;
1225+ }
1226+
1227+ /* shift the destination primary FIFO: */
1228+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1229+ dst_fifo0,
1230+ dst_fifo0_next,
1231+ dst_fifo0_bits,
1232+ 32,
1233+ dst_raw0,
1234+ dst_order);
1235+
1236+ /* iter #4 */
1237+
1238+ /* get a pixel from the source primary FIFO: */
1239+ pixel =
1240+ ((src_fifo0
1241+ >> (src_order == TME_ENDIAN_BIG
1242+ ? (32 - (src_bipp + (4 * src_bipp)))
1243+ : (4 * src_bipp))));
1244+
1245+ /* since source pixels are known at compile time to
1246+ not have subfields, map the source pixel into the
1247+ destination pixel: */
1248+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1249+
1250+ /* if the source buffer is not packed, and we just
1251+ read the last pixel on this source scanline: */
1252+ if (!src_packed
1253+ && ++src_x == src_width) {
1254+
1255+ /* calculate the number of bits between the
1256+ last bit of the last pixel and the first bit
1257+ of the first displayed pixel on the next
1258+ scanline. this is equal to the number of
1259+ pad bits plus bits for undisplayed pixels: */
1260+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1261+
1262+ /* while there are bits to shift: */
1263+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1264+
1265+ /* shift the source primary FIFO: */
1266+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1267+ src_fifo0,
1268+ src_fifo0_next,
1269+ src_fifo0_bits,
1270+ TME_MIN(src_off, 32),
1271+ src_raw0,
1272+ src_order);
1273+ }
1274+
1275+ /* we are now on the first pixel of the next scanline: */
1276+ src_x = 0;
1277+ }
1278+
1279+ /* put the pixel into the destination primary FIFO: */
1280+ dst_fifo0 |=
1281+ (pixel
1282+ << (dst_order == TME_ENDIAN_BIG
1283+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1284+ : (0 * dst_bipp)));
1285+
1286+ /* if the destination buffer is not packed, and we just
1287+ wrote the last pixel on this destination scanline: */
1288+ if (!dst_packed
1289+ && (dst_x += 1) == dst_width) {
1290+
1291+ /* calculate the number of bits between the
1292+ last bit of the last pixel and the first bit
1293+ of the first displayed pixel on the next
1294+ scanline. this is equal to the number of
1295+ pad bits plus bits for undisplayed pixels: */
1296+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1297+
1298+ /* while there are bits to shift: */
1299+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1300+
1301+ /* shift the destination primary FIFO: */
1302+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1303+ dst_fifo0,
1304+ dst_fifo0_next,
1305+ dst_fifo0_bits,
1306+ TME_MIN(dst_off, 32),
1307+ dst_raw0,
1308+ dst_order);
1309+ }
1310+
1311+ /* we are now on the first pixel of the next scanline: */
1312+ dst_x = 0;
1313+ }
1314+
1315+ /* shift the destination primary FIFO: */
1316+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1317+ dst_fifo0,
1318+ dst_fifo0_next,
1319+ dst_fifo0_bits,
1320+ 32,
1321+ dst_raw0,
1322+ dst_order);
1323+
1324+ /* iter #5 */
1325+
1326+ /* get a pixel from the source primary FIFO: */
1327+ pixel =
1328+ ((src_fifo0
1329+ >> (src_order == TME_ENDIAN_BIG
1330+ ? (32 - (src_bipp + (5 * src_bipp)))
1331+ : (5 * src_bipp))));
1332+
1333+ /* since source pixels are known at compile time to
1334+ not have subfields, map the source pixel into the
1335+ destination pixel: */
1336+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1337+
1338+ /* if the source buffer is not packed, and we just
1339+ read the last pixel on this source scanline: */
1340+ if (!src_packed
1341+ && ++src_x == src_width) {
1342+
1343+ /* calculate the number of bits between the
1344+ last bit of the last pixel and the first bit
1345+ of the first displayed pixel on the next
1346+ scanline. this is equal to the number of
1347+ pad bits plus bits for undisplayed pixels: */
1348+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1349+
1350+ /* while there are bits to shift: */
1351+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1352+
1353+ /* shift the source primary FIFO: */
1354+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1355+ src_fifo0,
1356+ src_fifo0_next,
1357+ src_fifo0_bits,
1358+ TME_MIN(src_off, 32),
1359+ src_raw0,
1360+ src_order);
1361+ }
1362+
1363+ /* we are now on the first pixel of the next scanline: */
1364+ src_x = 0;
1365+ }
1366+
1367+ /* put the pixel into the destination primary FIFO: */
1368+ dst_fifo0 |=
1369+ (pixel
1370+ << (dst_order == TME_ENDIAN_BIG
1371+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1372+ : (0 * dst_bipp)));
1373+
1374+ /* if the destination buffer is not packed, and we just
1375+ wrote the last pixel on this destination scanline: */
1376+ if (!dst_packed
1377+ && (dst_x += 1) == dst_width) {
1378+
1379+ /* calculate the number of bits between the
1380+ last bit of the last pixel and the first bit
1381+ of the first displayed pixel on the next
1382+ scanline. this is equal to the number of
1383+ pad bits plus bits for undisplayed pixels: */
1384+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1385+
1386+ /* while there are bits to shift: */
1387+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1388+
1389+ /* shift the destination primary FIFO: */
1390+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1391+ dst_fifo0,
1392+ dst_fifo0_next,
1393+ dst_fifo0_bits,
1394+ TME_MIN(dst_off, 32),
1395+ dst_raw0,
1396+ dst_order);
1397+ }
1398+
1399+ /* we are now on the first pixel of the next scanline: */
1400+ dst_x = 0;
1401+ }
1402+
1403+ /* shift the destination primary FIFO: */
1404+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1405+ dst_fifo0,
1406+ dst_fifo0_next,
1407+ dst_fifo0_bits,
1408+ 32,
1409+ dst_raw0,
1410+ dst_order);
1411+
1412+ /* iter #6 */
1413+
1414+ /* get a pixel from the source primary FIFO: */
1415+ pixel =
1416+ ((src_fifo0
1417+ >> (src_order == TME_ENDIAN_BIG
1418+ ? (32 - (src_bipp + (6 * src_bipp)))
1419+ : (6 * src_bipp))));
1420+
1421+ /* since source pixels are known at compile time to
1422+ not have subfields, map the source pixel into the
1423+ destination pixel: */
1424+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1425+
1426+ /* if the source buffer is not packed, and we just
1427+ read the last pixel on this source scanline: */
1428+ if (!src_packed
1429+ && ++src_x == src_width) {
1430+
1431+ /* calculate the number of bits between the
1432+ last bit of the last pixel and the first bit
1433+ of the first displayed pixel on the next
1434+ scanline. this is equal to the number of
1435+ pad bits plus bits for undisplayed pixels: */
1436+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1437+
1438+ /* while there are bits to shift: */
1439+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1440+
1441+ /* shift the source primary FIFO: */
1442+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1443+ src_fifo0,
1444+ src_fifo0_next,
1445+ src_fifo0_bits,
1446+ TME_MIN(src_off, 32),
1447+ src_raw0,
1448+ src_order);
1449+ }
1450+
1451+ /* we are now on the first pixel of the next scanline: */
1452+ src_x = 0;
1453+ }
1454+
1455+ /* put the pixel into the destination primary FIFO: */
1456+ dst_fifo0 |=
1457+ (pixel
1458+ << (dst_order == TME_ENDIAN_BIG
1459+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1460+ : (0 * dst_bipp)));
1461+
1462+ /* if the destination buffer is not packed, and we just
1463+ wrote the last pixel on this destination scanline: */
1464+ if (!dst_packed
1465+ && (dst_x += 1) == dst_width) {
1466+
1467+ /* calculate the number of bits between the
1468+ last bit of the last pixel and the first bit
1469+ of the first displayed pixel on the next
1470+ scanline. this is equal to the number of
1471+ pad bits plus bits for undisplayed pixels: */
1472+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1473+
1474+ /* while there are bits to shift: */
1475+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1476+
1477+ /* shift the destination primary FIFO: */
1478+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1479+ dst_fifo0,
1480+ dst_fifo0_next,
1481+ dst_fifo0_bits,
1482+ TME_MIN(dst_off, 32),
1483+ dst_raw0,
1484+ dst_order);
1485+ }
1486+
1487+ /* we are now on the first pixel of the next scanline: */
1488+ dst_x = 0;
1489+ }
1490+
1491+ /* shift the destination primary FIFO: */
1492+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1493+ dst_fifo0,
1494+ dst_fifo0_next,
1495+ dst_fifo0_bits,
1496+ 32,
1497+ dst_raw0,
1498+ dst_order);
1499+
1500+ /* iter #7 */
1501+
1502+ /* get a pixel from the source primary FIFO: */
1503+ pixel =
1504+ ((src_fifo0
1505+ >> (src_order == TME_ENDIAN_BIG
1506+ ? (32 - (src_bipp + (7 * src_bipp)))
1507+ : (7 * src_bipp))));
1508+
1509+ /* since source pixels are known at compile time to
1510+ not have subfields, map the source pixel into the
1511+ destination pixel: */
1512+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1513+
1514+ /* if the source buffer is not packed, and we just
1515+ read the last pixel on this source scanline: */
1516+ if (!src_packed
1517+ && ++src_x == src_width) {
1518+
1519+ /* calculate the number of bits between the
1520+ last bit of the last pixel and the first bit
1521+ of the first displayed pixel on the next
1522+ scanline. this is equal to the number of
1523+ pad bits plus bits for undisplayed pixels: */
1524+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1525+
1526+ /* while there are bits to shift: */
1527+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1528+
1529+ /* shift the source primary FIFO: */
1530+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1531+ src_fifo0,
1532+ src_fifo0_next,
1533+ src_fifo0_bits,
1534+ TME_MIN(src_off, 32),
1535+ src_raw0,
1536+ src_order);
1537+ }
1538+
1539+ /* we are now on the first pixel of the next scanline: */
1540+ src_x = 0;
1541+ }
1542+
1543+ /* put the pixel into the destination primary FIFO: */
1544+ dst_fifo0 |=
1545+ (pixel
1546+ << (dst_order == TME_ENDIAN_BIG
1547+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1548+ : (0 * dst_bipp)));
1549+
1550+ /* if the destination buffer is not packed, and we just
1551+ wrote the last pixel on this destination scanline: */
1552+ if (!dst_packed
1553+ && (dst_x += 1) == dst_width) {
1554+
1555+ /* calculate the number of bits between the
1556+ last bit of the last pixel and the first bit
1557+ of the first displayed pixel on the next
1558+ scanline. this is equal to the number of
1559+ pad bits plus bits for undisplayed pixels: */
1560+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1561+
1562+ /* while there are bits to shift: */
1563+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1564+
1565+ /* shift the destination primary FIFO: */
1566+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1567+ dst_fifo0,
1568+ dst_fifo0_next,
1569+ dst_fifo0_bits,
1570+ TME_MIN(dst_off, 32),
1571+ dst_raw0,
1572+ dst_order);
1573+ }
1574+
1575+ /* we are now on the first pixel of the next scanline: */
1576+ dst_x = 0;
1577+ }
1578+
1579+ /* shift the destination primary FIFO: */
1580+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1581+ dst_fifo0,
1582+ dst_fifo0_next,
1583+ dst_fifo0_bits,
1584+ 32,
1585+ dst_raw0,
1586+ dst_order);
1587+
1588+ /* iter #8 */
1589+
1590+ /* get a pixel from the source primary FIFO: */
1591+ pixel =
1592+ ((src_fifo0
1593+ >> (src_order == TME_ENDIAN_BIG
1594+ ? (32 - (src_bipp + (8 * src_bipp)))
1595+ : (8 * src_bipp))));
1596+
1597+ /* since source pixels are known at compile time to
1598+ not have subfields, map the source pixel into the
1599+ destination pixel: */
1600+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1601+
1602+ /* if the source buffer is not packed, and we just
1603+ read the last pixel on this source scanline: */
1604+ if (!src_packed
1605+ && ++src_x == src_width) {
1606+
1607+ /* calculate the number of bits between the
1608+ last bit of the last pixel and the first bit
1609+ of the first displayed pixel on the next
1610+ scanline. this is equal to the number of
1611+ pad bits plus bits for undisplayed pixels: */
1612+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1613+
1614+ /* while there are bits to shift: */
1615+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1616+
1617+ /* shift the source primary FIFO: */
1618+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1619+ src_fifo0,
1620+ src_fifo0_next,
1621+ src_fifo0_bits,
1622+ TME_MIN(src_off, 32),
1623+ src_raw0,
1624+ src_order);
1625+ }
1626+
1627+ /* we are now on the first pixel of the next scanline: */
1628+ src_x = 0;
1629+ }
1630+
1631+ /* put the pixel into the destination primary FIFO: */
1632+ dst_fifo0 |=
1633+ (pixel
1634+ << (dst_order == TME_ENDIAN_BIG
1635+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1636+ : (0 * dst_bipp)));
1637+
1638+ /* if the destination buffer is not packed, and we just
1639+ wrote the last pixel on this destination scanline: */
1640+ if (!dst_packed
1641+ && (dst_x += 1) == dst_width) {
1642+
1643+ /* calculate the number of bits between the
1644+ last bit of the last pixel and the first bit
1645+ of the first displayed pixel on the next
1646+ scanline. this is equal to the number of
1647+ pad bits plus bits for undisplayed pixels: */
1648+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1649+
1650+ /* while there are bits to shift: */
1651+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1652+
1653+ /* shift the destination primary FIFO: */
1654+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1655+ dst_fifo0,
1656+ dst_fifo0_next,
1657+ dst_fifo0_bits,
1658+ TME_MIN(dst_off, 32),
1659+ dst_raw0,
1660+ dst_order);
1661+ }
1662+
1663+ /* we are now on the first pixel of the next scanline: */
1664+ dst_x = 0;
1665+ }
1666+
1667+ /* shift the destination primary FIFO: */
1668+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1669+ dst_fifo0,
1670+ dst_fifo0_next,
1671+ dst_fifo0_bits,
1672+ 32,
1673+ dst_raw0,
1674+ dst_order);
1675+
1676+ /* iter #9 */
1677+
1678+ /* get a pixel from the source primary FIFO: */
1679+ pixel =
1680+ ((src_fifo0
1681+ >> (src_order == TME_ENDIAN_BIG
1682+ ? (32 - (src_bipp + (9 * src_bipp)))
1683+ : (9 * src_bipp))));
1684+
1685+ /* since source pixels are known at compile time to
1686+ not have subfields, map the source pixel into the
1687+ destination pixel: */
1688+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1689+
1690+ /* if the source buffer is not packed, and we just
1691+ read the last pixel on this source scanline: */
1692+ if (!src_packed
1693+ && ++src_x == src_width) {
1694+
1695+ /* calculate the number of bits between the
1696+ last bit of the last pixel and the first bit
1697+ of the first displayed pixel on the next
1698+ scanline. this is equal to the number of
1699+ pad bits plus bits for undisplayed pixels: */
1700+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1701+
1702+ /* while there are bits to shift: */
1703+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1704+
1705+ /* shift the source primary FIFO: */
1706+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1707+ src_fifo0,
1708+ src_fifo0_next,
1709+ src_fifo0_bits,
1710+ TME_MIN(src_off, 32),
1711+ src_raw0,
1712+ src_order);
1713+ }
1714+
1715+ /* we are now on the first pixel of the next scanline: */
1716+ src_x = 0;
1717+ }
1718+
1719+ /* put the pixel into the destination primary FIFO: */
1720+ dst_fifo0 |=
1721+ (pixel
1722+ << (dst_order == TME_ENDIAN_BIG
1723+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1724+ : (0 * dst_bipp)));
1725+
1726+ /* if the destination buffer is not packed, and we just
1727+ wrote the last pixel on this destination scanline: */
1728+ if (!dst_packed
1729+ && (dst_x += 1) == dst_width) {
1730+
1731+ /* calculate the number of bits between the
1732+ last bit of the last pixel and the first bit
1733+ of the first displayed pixel on the next
1734+ scanline. this is equal to the number of
1735+ pad bits plus bits for undisplayed pixels: */
1736+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1737+
1738+ /* while there are bits to shift: */
1739+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1740+
1741+ /* shift the destination primary FIFO: */
1742+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1743+ dst_fifo0,
1744+ dst_fifo0_next,
1745+ dst_fifo0_bits,
1746+ TME_MIN(dst_off, 32),
1747+ dst_raw0,
1748+ dst_order);
1749+ }
1750+
1751+ /* we are now on the first pixel of the next scanline: */
1752+ dst_x = 0;
1753+ }
1754+
1755+ /* shift the destination primary FIFO: */
1756+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1757+ dst_fifo0,
1758+ dst_fifo0_next,
1759+ dst_fifo0_bits,
1760+ 32,
1761+ dst_raw0,
1762+ dst_order);
1763+
1764+ /* iter #10 */
1765+
1766+ /* get a pixel from the source primary FIFO: */
1767+ pixel =
1768+ ((src_fifo0
1769+ >> (src_order == TME_ENDIAN_BIG
1770+ ? (32 - (src_bipp + (10 * src_bipp)))
1771+ : (10 * src_bipp))));
1772+
1773+ /* since source pixels are known at compile time to
1774+ not have subfields, map the source pixel into the
1775+ destination pixel: */
1776+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1777+
1778+ /* if the source buffer is not packed, and we just
1779+ read the last pixel on this source scanline: */
1780+ if (!src_packed
1781+ && ++src_x == src_width) {
1782+
1783+ /* calculate the number of bits between the
1784+ last bit of the last pixel and the first bit
1785+ of the first displayed pixel on the next
1786+ scanline. this is equal to the number of
1787+ pad bits plus bits for undisplayed pixels: */
1788+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1789+
1790+ /* while there are bits to shift: */
1791+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1792+
1793+ /* shift the source primary FIFO: */
1794+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1795+ src_fifo0,
1796+ src_fifo0_next,
1797+ src_fifo0_bits,
1798+ TME_MIN(src_off, 32),
1799+ src_raw0,
1800+ src_order);
1801+ }
1802+
1803+ /* we are now on the first pixel of the next scanline: */
1804+ src_x = 0;
1805+ }
1806+
1807+ /* put the pixel into the destination primary FIFO: */
1808+ dst_fifo0 |=
1809+ (pixel
1810+ << (dst_order == TME_ENDIAN_BIG
1811+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1812+ : (0 * dst_bipp)));
1813+
1814+ /* if the destination buffer is not packed, and we just
1815+ wrote the last pixel on this destination scanline: */
1816+ if (!dst_packed
1817+ && (dst_x += 1) == dst_width) {
1818+
1819+ /* calculate the number of bits between the
1820+ last bit of the last pixel and the first bit
1821+ of the first displayed pixel on the next
1822+ scanline. this is equal to the number of
1823+ pad bits plus bits for undisplayed pixels: */
1824+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1825+
1826+ /* while there are bits to shift: */
1827+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1828+
1829+ /* shift the destination primary FIFO: */
1830+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1831+ dst_fifo0,
1832+ dst_fifo0_next,
1833+ dst_fifo0_bits,
1834+ TME_MIN(dst_off, 32),
1835+ dst_raw0,
1836+ dst_order);
1837+ }
1838+
1839+ /* we are now on the first pixel of the next scanline: */
1840+ dst_x = 0;
1841+ }
1842+
1843+ /* shift the destination primary FIFO: */
1844+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1845+ dst_fifo0,
1846+ dst_fifo0_next,
1847+ dst_fifo0_bits,
1848+ 32,
1849+ dst_raw0,
1850+ dst_order);
1851+
1852+ /* iter #11 */
1853+
1854+ /* get a pixel from the source primary FIFO: */
1855+ pixel =
1856+ ((src_fifo0
1857+ >> (src_order == TME_ENDIAN_BIG
1858+ ? (32 - (src_bipp + (11 * src_bipp)))
1859+ : (11 * src_bipp))));
1860+
1861+ /* since source pixels are known at compile time to
1862+ not have subfields, map the source pixel into the
1863+ destination pixel: */
1864+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1865+
1866+ /* if the source buffer is not packed, and we just
1867+ read the last pixel on this source scanline: */
1868+ if (!src_packed
1869+ && ++src_x == src_width) {
1870+
1871+ /* calculate the number of bits between the
1872+ last bit of the last pixel and the first bit
1873+ of the first displayed pixel on the next
1874+ scanline. this is equal to the number of
1875+ pad bits plus bits for undisplayed pixels: */
1876+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1877+
1878+ /* while there are bits to shift: */
1879+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1880+
1881+ /* shift the source primary FIFO: */
1882+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1883+ src_fifo0,
1884+ src_fifo0_next,
1885+ src_fifo0_bits,
1886+ TME_MIN(src_off, 32),
1887+ src_raw0,
1888+ src_order);
1889+ }
1890+
1891+ /* we are now on the first pixel of the next scanline: */
1892+ src_x = 0;
1893+ }
1894+
1895+ /* put the pixel into the destination primary FIFO: */
1896+ dst_fifo0 |=
1897+ (pixel
1898+ << (dst_order == TME_ENDIAN_BIG
1899+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1900+ : (0 * dst_bipp)));
1901+
1902+ /* if the destination buffer is not packed, and we just
1903+ wrote the last pixel on this destination scanline: */
1904+ if (!dst_packed
1905+ && (dst_x += 1) == dst_width) {
1906+
1907+ /* calculate the number of bits between the
1908+ last bit of the last pixel and the first bit
1909+ of the first displayed pixel on the next
1910+ scanline. this is equal to the number of
1911+ pad bits plus bits for undisplayed pixels: */
1912+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
1913+
1914+ /* while there are bits to shift: */
1915+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
1916+
1917+ /* shift the destination primary FIFO: */
1918+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1919+ dst_fifo0,
1920+ dst_fifo0_next,
1921+ dst_fifo0_bits,
1922+ TME_MIN(dst_off, 32),
1923+ dst_raw0,
1924+ dst_order);
1925+ }
1926+
1927+ /* we are now on the first pixel of the next scanline: */
1928+ dst_x = 0;
1929+ }
1930+
1931+ /* shift the destination primary FIFO: */
1932+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
1933+ dst_fifo0,
1934+ dst_fifo0_next,
1935+ dst_fifo0_bits,
1936+ 32,
1937+ dst_raw0,
1938+ dst_order);
1939+
1940+ /* iter #12 */
1941+
1942+ /* get a pixel from the source primary FIFO: */
1943+ pixel =
1944+ ((src_fifo0
1945+ >> (src_order == TME_ENDIAN_BIG
1946+ ? (32 - (src_bipp + (12 * src_bipp)))
1947+ : (12 * src_bipp))));
1948+
1949+ /* since source pixels are known at compile time to
1950+ not have subfields, map the source pixel into the
1951+ destination pixel: */
1952+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
1953+
1954+ /* if the source buffer is not packed, and we just
1955+ read the last pixel on this source scanline: */
1956+ if (!src_packed
1957+ && ++src_x == src_width) {
1958+
1959+ /* calculate the number of bits between the
1960+ last bit of the last pixel and the first bit
1961+ of the first displayed pixel on the next
1962+ scanline. this is equal to the number of
1963+ pad bits plus bits for undisplayed pixels: */
1964+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
1965+
1966+ /* while there are bits to shift: */
1967+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
1968+
1969+ /* shift the source primary FIFO: */
1970+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
1971+ src_fifo0,
1972+ src_fifo0_next,
1973+ src_fifo0_bits,
1974+ TME_MIN(src_off, 32),
1975+ src_raw0,
1976+ src_order);
1977+ }
1978+
1979+ /* we are now on the first pixel of the next scanline: */
1980+ src_x = 0;
1981+ }
1982+
1983+ /* put the pixel into the destination primary FIFO: */
1984+ dst_fifo0 |=
1985+ (pixel
1986+ << (dst_order == TME_ENDIAN_BIG
1987+ ? ((32 - dst_bipp) - (0 * dst_bipp))
1988+ : (0 * dst_bipp)));
1989+
1990+ /* if the destination buffer is not packed, and we just
1991+ wrote the last pixel on this destination scanline: */
1992+ if (!dst_packed
1993+ && (dst_x += 1) == dst_width) {
1994+
1995+ /* calculate the number of bits between the
1996+ last bit of the last pixel and the first bit
1997+ of the first displayed pixel on the next
1998+ scanline. this is equal to the number of
1999+ pad bits plus bits for undisplayed pixels: */
2000+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2001+
2002+ /* while there are bits to shift: */
2003+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2004+
2005+ /* shift the destination primary FIFO: */
2006+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2007+ dst_fifo0,
2008+ dst_fifo0_next,
2009+ dst_fifo0_bits,
2010+ TME_MIN(dst_off, 32),
2011+ dst_raw0,
2012+ dst_order);
2013+ }
2014+
2015+ /* we are now on the first pixel of the next scanline: */
2016+ dst_x = 0;
2017+ }
2018+
2019+ /* shift the destination primary FIFO: */
2020+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2021+ dst_fifo0,
2022+ dst_fifo0_next,
2023+ dst_fifo0_bits,
2024+ 32,
2025+ dst_raw0,
2026+ dst_order);
2027+
2028+ /* iter #13 */
2029+
2030+ /* get a pixel from the source primary FIFO: */
2031+ pixel =
2032+ ((src_fifo0
2033+ >> (src_order == TME_ENDIAN_BIG
2034+ ? (32 - (src_bipp + (13 * src_bipp)))
2035+ : (13 * src_bipp))));
2036+
2037+ /* since source pixels are known at compile time to
2038+ not have subfields, map the source pixel into the
2039+ destination pixel: */
2040+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2041+
2042+ /* if the source buffer is not packed, and we just
2043+ read the last pixel on this source scanline: */
2044+ if (!src_packed
2045+ && ++src_x == src_width) {
2046+
2047+ /* calculate the number of bits between the
2048+ last bit of the last pixel and the first bit
2049+ of the first displayed pixel on the next
2050+ scanline. this is equal to the number of
2051+ pad bits plus bits for undisplayed pixels: */
2052+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2053+
2054+ /* while there are bits to shift: */
2055+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2056+
2057+ /* shift the source primary FIFO: */
2058+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2059+ src_fifo0,
2060+ src_fifo0_next,
2061+ src_fifo0_bits,
2062+ TME_MIN(src_off, 32),
2063+ src_raw0,
2064+ src_order);
2065+ }
2066+
2067+ /* we are now on the first pixel of the next scanline: */
2068+ src_x = 0;
2069+ }
2070+
2071+ /* put the pixel into the destination primary FIFO: */
2072+ dst_fifo0 |=
2073+ (pixel
2074+ << (dst_order == TME_ENDIAN_BIG
2075+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2076+ : (0 * dst_bipp)));
2077+
2078+ /* if the destination buffer is not packed, and we just
2079+ wrote the last pixel on this destination scanline: */
2080+ if (!dst_packed
2081+ && (dst_x += 1) == dst_width) {
2082+
2083+ /* calculate the number of bits between the
2084+ last bit of the last pixel and the first bit
2085+ of the first displayed pixel on the next
2086+ scanline. this is equal to the number of
2087+ pad bits plus bits for undisplayed pixels: */
2088+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2089+
2090+ /* while there are bits to shift: */
2091+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2092+
2093+ /* shift the destination primary FIFO: */
2094+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2095+ dst_fifo0,
2096+ dst_fifo0_next,
2097+ dst_fifo0_bits,
2098+ TME_MIN(dst_off, 32),
2099+ dst_raw0,
2100+ dst_order);
2101+ }
2102+
2103+ /* we are now on the first pixel of the next scanline: */
2104+ dst_x = 0;
2105+ }
2106+
2107+ /* shift the destination primary FIFO: */
2108+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2109+ dst_fifo0,
2110+ dst_fifo0_next,
2111+ dst_fifo0_bits,
2112+ 32,
2113+ dst_raw0,
2114+ dst_order);
2115+
2116+ /* iter #14 */
2117+
2118+ /* get a pixel from the source primary FIFO: */
2119+ pixel =
2120+ ((src_fifo0
2121+ >> (src_order == TME_ENDIAN_BIG
2122+ ? (32 - (src_bipp + (14 * src_bipp)))
2123+ : (14 * src_bipp))));
2124+
2125+ /* since source pixels are known at compile time to
2126+ not have subfields, map the source pixel into the
2127+ destination pixel: */
2128+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2129+
2130+ /* if the source buffer is not packed, and we just
2131+ read the last pixel on this source scanline: */
2132+ if (!src_packed
2133+ && ++src_x == src_width) {
2134+
2135+ /* calculate the number of bits between the
2136+ last bit of the last pixel and the first bit
2137+ of the first displayed pixel on the next
2138+ scanline. this is equal to the number of
2139+ pad bits plus bits for undisplayed pixels: */
2140+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2141+
2142+ /* while there are bits to shift: */
2143+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2144+
2145+ /* shift the source primary FIFO: */
2146+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2147+ src_fifo0,
2148+ src_fifo0_next,
2149+ src_fifo0_bits,
2150+ TME_MIN(src_off, 32),
2151+ src_raw0,
2152+ src_order);
2153+ }
2154+
2155+ /* we are now on the first pixel of the next scanline: */
2156+ src_x = 0;
2157+ }
2158+
2159+ /* put the pixel into the destination primary FIFO: */
2160+ dst_fifo0 |=
2161+ (pixel
2162+ << (dst_order == TME_ENDIAN_BIG
2163+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2164+ : (0 * dst_bipp)));
2165+
2166+ /* if the destination buffer is not packed, and we just
2167+ wrote the last pixel on this destination scanline: */
2168+ if (!dst_packed
2169+ && (dst_x += 1) == dst_width) {
2170+
2171+ /* calculate the number of bits between the
2172+ last bit of the last pixel and the first bit
2173+ of the first displayed pixel on the next
2174+ scanline. this is equal to the number of
2175+ pad bits plus bits for undisplayed pixels: */
2176+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2177+
2178+ /* while there are bits to shift: */
2179+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2180+
2181+ /* shift the destination primary FIFO: */
2182+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2183+ dst_fifo0,
2184+ dst_fifo0_next,
2185+ dst_fifo0_bits,
2186+ TME_MIN(dst_off, 32),
2187+ dst_raw0,
2188+ dst_order);
2189+ }
2190+
2191+ /* we are now on the first pixel of the next scanline: */
2192+ dst_x = 0;
2193+ }
2194+
2195+ /* shift the destination primary FIFO: */
2196+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2197+ dst_fifo0,
2198+ dst_fifo0_next,
2199+ dst_fifo0_bits,
2200+ 32,
2201+ dst_raw0,
2202+ dst_order);
2203+
2204+ /* iter #15 */
2205+
2206+ /* get a pixel from the source primary FIFO: */
2207+ pixel =
2208+ ((src_fifo0
2209+ >> (src_order == TME_ENDIAN_BIG
2210+ ? (32 - (src_bipp + (15 * src_bipp)))
2211+ : (15 * src_bipp))));
2212+
2213+ /* since source pixels are known at compile time to
2214+ not have subfields, map the source pixel into the
2215+ destination pixel: */
2216+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2217+
2218+ /* if the source buffer is not packed, and we just
2219+ read the last pixel on this source scanline: */
2220+ if (!src_packed
2221+ && ++src_x == src_width) {
2222+
2223+ /* calculate the number of bits between the
2224+ last bit of the last pixel and the first bit
2225+ of the first displayed pixel on the next
2226+ scanline. this is equal to the number of
2227+ pad bits plus bits for undisplayed pixels: */
2228+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2229+
2230+ /* while there are bits to shift: */
2231+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2232+
2233+ /* shift the source primary FIFO: */
2234+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2235+ src_fifo0,
2236+ src_fifo0_next,
2237+ src_fifo0_bits,
2238+ TME_MIN(src_off, 32),
2239+ src_raw0,
2240+ src_order);
2241+ }
2242+
2243+ /* we are now on the first pixel of the next scanline: */
2244+ src_x = 0;
2245+ }
2246+
2247+ /* put the pixel into the destination primary FIFO: */
2248+ dst_fifo0 |=
2249+ (pixel
2250+ << (dst_order == TME_ENDIAN_BIG
2251+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2252+ : (0 * dst_bipp)));
2253+
2254+ /* if the destination buffer is not packed, and we just
2255+ wrote the last pixel on this destination scanline: */
2256+ if (!dst_packed
2257+ && (dst_x += 1) == dst_width) {
2258+
2259+ /* calculate the number of bits between the
2260+ last bit of the last pixel and the first bit
2261+ of the first displayed pixel on the next
2262+ scanline. this is equal to the number of
2263+ pad bits plus bits for undisplayed pixels: */
2264+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2265+
2266+ /* while there are bits to shift: */
2267+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2268+
2269+ /* shift the destination primary FIFO: */
2270+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2271+ dst_fifo0,
2272+ dst_fifo0_next,
2273+ dst_fifo0_bits,
2274+ TME_MIN(dst_off, 32),
2275+ dst_raw0,
2276+ dst_order);
2277+ }
2278+
2279+ /* we are now on the first pixel of the next scanline: */
2280+ dst_x = 0;
2281+ }
2282+
2283+ /* shift the destination primary FIFO: */
2284+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2285+ dst_fifo0,
2286+ dst_fifo0_next,
2287+ dst_fifo0_bits,
2288+ 32,
2289+ dst_raw0,
2290+ dst_order);
2291+
2292+ /* iter #16 */
2293+
2294+ /* get a pixel from the source primary FIFO: */
2295+ pixel =
2296+ ((src_fifo0
2297+ >> (src_order == TME_ENDIAN_BIG
2298+ ? (32 - (src_bipp + (16 * src_bipp)))
2299+ : (16 * src_bipp))));
2300+
2301+ /* since source pixels are known at compile time to
2302+ not have subfields, map the source pixel into the
2303+ destination pixel: */
2304+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2305+
2306+ /* if the source buffer is not packed, and we just
2307+ read the last pixel on this source scanline: */
2308+ if (!src_packed
2309+ && ++src_x == src_width) {
2310+
2311+ /* calculate the number of bits between the
2312+ last bit of the last pixel and the first bit
2313+ of the first displayed pixel on the next
2314+ scanline. this is equal to the number of
2315+ pad bits plus bits for undisplayed pixels: */
2316+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2317+
2318+ /* while there are bits to shift: */
2319+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2320+
2321+ /* shift the source primary FIFO: */
2322+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2323+ src_fifo0,
2324+ src_fifo0_next,
2325+ src_fifo0_bits,
2326+ TME_MIN(src_off, 32),
2327+ src_raw0,
2328+ src_order);
2329+ }
2330+
2331+ /* we are now on the first pixel of the next scanline: */
2332+ src_x = 0;
2333+ }
2334+
2335+ /* put the pixel into the destination primary FIFO: */
2336+ dst_fifo0 |=
2337+ (pixel
2338+ << (dst_order == TME_ENDIAN_BIG
2339+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2340+ : (0 * dst_bipp)));
2341+
2342+ /* if the destination buffer is not packed, and we just
2343+ wrote the last pixel on this destination scanline: */
2344+ if (!dst_packed
2345+ && (dst_x += 1) == dst_width) {
2346+
2347+ /* calculate the number of bits between the
2348+ last bit of the last pixel and the first bit
2349+ of the first displayed pixel on the next
2350+ scanline. this is equal to the number of
2351+ pad bits plus bits for undisplayed pixels: */
2352+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2353+
2354+ /* while there are bits to shift: */
2355+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2356+
2357+ /* shift the destination primary FIFO: */
2358+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2359+ dst_fifo0,
2360+ dst_fifo0_next,
2361+ dst_fifo0_bits,
2362+ TME_MIN(dst_off, 32),
2363+ dst_raw0,
2364+ dst_order);
2365+ }
2366+
2367+ /* we are now on the first pixel of the next scanline: */
2368+ dst_x = 0;
2369+ }
2370+
2371+ /* shift the destination primary FIFO: */
2372+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2373+ dst_fifo0,
2374+ dst_fifo0_next,
2375+ dst_fifo0_bits,
2376+ 32,
2377+ dst_raw0,
2378+ dst_order);
2379+
2380+ /* iter #17 */
2381+
2382+ /* get a pixel from the source primary FIFO: */
2383+ pixel =
2384+ ((src_fifo0
2385+ >> (src_order == TME_ENDIAN_BIG
2386+ ? (32 - (src_bipp + (17 * src_bipp)))
2387+ : (17 * src_bipp))));
2388+
2389+ /* since source pixels are known at compile time to
2390+ not have subfields, map the source pixel into the
2391+ destination pixel: */
2392+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2393+
2394+ /* if the source buffer is not packed, and we just
2395+ read the last pixel on this source scanline: */
2396+ if (!src_packed
2397+ && ++src_x == src_width) {
2398+
2399+ /* calculate the number of bits between the
2400+ last bit of the last pixel and the first bit
2401+ of the first displayed pixel on the next
2402+ scanline. this is equal to the number of
2403+ pad bits plus bits for undisplayed pixels: */
2404+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2405+
2406+ /* while there are bits to shift: */
2407+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2408+
2409+ /* shift the source primary FIFO: */
2410+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2411+ src_fifo0,
2412+ src_fifo0_next,
2413+ src_fifo0_bits,
2414+ TME_MIN(src_off, 32),
2415+ src_raw0,
2416+ src_order);
2417+ }
2418+
2419+ /* we are now on the first pixel of the next scanline: */
2420+ src_x = 0;
2421+ }
2422+
2423+ /* put the pixel into the destination primary FIFO: */
2424+ dst_fifo0 |=
2425+ (pixel
2426+ << (dst_order == TME_ENDIAN_BIG
2427+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2428+ : (0 * dst_bipp)));
2429+
2430+ /* if the destination buffer is not packed, and we just
2431+ wrote the last pixel on this destination scanline: */
2432+ if (!dst_packed
2433+ && (dst_x += 1) == dst_width) {
2434+
2435+ /* calculate the number of bits between the
2436+ last bit of the last pixel and the first bit
2437+ of the first displayed pixel on the next
2438+ scanline. this is equal to the number of
2439+ pad bits plus bits for undisplayed pixels: */
2440+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2441+
2442+ /* while there are bits to shift: */
2443+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2444+
2445+ /* shift the destination primary FIFO: */
2446+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2447+ dst_fifo0,
2448+ dst_fifo0_next,
2449+ dst_fifo0_bits,
2450+ TME_MIN(dst_off, 32),
2451+ dst_raw0,
2452+ dst_order);
2453+ }
2454+
2455+ /* we are now on the first pixel of the next scanline: */
2456+ dst_x = 0;
2457+ }
2458+
2459+ /* shift the destination primary FIFO: */
2460+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2461+ dst_fifo0,
2462+ dst_fifo0_next,
2463+ dst_fifo0_bits,
2464+ 32,
2465+ dst_raw0,
2466+ dst_order);
2467+
2468+ /* iter #18 */
2469+
2470+ /* get a pixel from the source primary FIFO: */
2471+ pixel =
2472+ ((src_fifo0
2473+ >> (src_order == TME_ENDIAN_BIG
2474+ ? (32 - (src_bipp + (18 * src_bipp)))
2475+ : (18 * src_bipp))));
2476+
2477+ /* since source pixels are known at compile time to
2478+ not have subfields, map the source pixel into the
2479+ destination pixel: */
2480+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2481+
2482+ /* if the source buffer is not packed, and we just
2483+ read the last pixel on this source scanline: */
2484+ if (!src_packed
2485+ && ++src_x == src_width) {
2486+
2487+ /* calculate the number of bits between the
2488+ last bit of the last pixel and the first bit
2489+ of the first displayed pixel on the next
2490+ scanline. this is equal to the number of
2491+ pad bits plus bits for undisplayed pixels: */
2492+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2493+
2494+ /* while there are bits to shift: */
2495+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2496+
2497+ /* shift the source primary FIFO: */
2498+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2499+ src_fifo0,
2500+ src_fifo0_next,
2501+ src_fifo0_bits,
2502+ TME_MIN(src_off, 32),
2503+ src_raw0,
2504+ src_order);
2505+ }
2506+
2507+ /* we are now on the first pixel of the next scanline: */
2508+ src_x = 0;
2509+ }
2510+
2511+ /* put the pixel into the destination primary FIFO: */
2512+ dst_fifo0 |=
2513+ (pixel
2514+ << (dst_order == TME_ENDIAN_BIG
2515+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2516+ : (0 * dst_bipp)));
2517+
2518+ /* if the destination buffer is not packed, and we just
2519+ wrote the last pixel on this destination scanline: */
2520+ if (!dst_packed
2521+ && (dst_x += 1) == dst_width) {
2522+
2523+ /* calculate the number of bits between the
2524+ last bit of the last pixel and the first bit
2525+ of the first displayed pixel on the next
2526+ scanline. this is equal to the number of
2527+ pad bits plus bits for undisplayed pixels: */
2528+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2529+
2530+ /* while there are bits to shift: */
2531+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2532+
2533+ /* shift the destination primary FIFO: */
2534+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2535+ dst_fifo0,
2536+ dst_fifo0_next,
2537+ dst_fifo0_bits,
2538+ TME_MIN(dst_off, 32),
2539+ dst_raw0,
2540+ dst_order);
2541+ }
2542+
2543+ /* we are now on the first pixel of the next scanline: */
2544+ dst_x = 0;
2545+ }
2546+
2547+ /* shift the destination primary FIFO: */
2548+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2549+ dst_fifo0,
2550+ dst_fifo0_next,
2551+ dst_fifo0_bits,
2552+ 32,
2553+ dst_raw0,
2554+ dst_order);
2555+
2556+ /* iter #19 */
2557+
2558+ /* get a pixel from the source primary FIFO: */
2559+ pixel =
2560+ ((src_fifo0
2561+ >> (src_order == TME_ENDIAN_BIG
2562+ ? (32 - (src_bipp + (19 * src_bipp)))
2563+ : (19 * src_bipp))));
2564+
2565+ /* since source pixels are known at compile time to
2566+ not have subfields, map the source pixel into the
2567+ destination pixel: */
2568+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2569+
2570+ /* if the source buffer is not packed, and we just
2571+ read the last pixel on this source scanline: */
2572+ if (!src_packed
2573+ && ++src_x == src_width) {
2574+
2575+ /* calculate the number of bits between the
2576+ last bit of the last pixel and the first bit
2577+ of the first displayed pixel on the next
2578+ scanline. this is equal to the number of
2579+ pad bits plus bits for undisplayed pixels: */
2580+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2581+
2582+ /* while there are bits to shift: */
2583+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2584+
2585+ /* shift the source primary FIFO: */
2586+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2587+ src_fifo0,
2588+ src_fifo0_next,
2589+ src_fifo0_bits,
2590+ TME_MIN(src_off, 32),
2591+ src_raw0,
2592+ src_order);
2593+ }
2594+
2595+ /* we are now on the first pixel of the next scanline: */
2596+ src_x = 0;
2597+ }
2598+
2599+ /* put the pixel into the destination primary FIFO: */
2600+ dst_fifo0 |=
2601+ (pixel
2602+ << (dst_order == TME_ENDIAN_BIG
2603+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2604+ : (0 * dst_bipp)));
2605+
2606+ /* if the destination buffer is not packed, and we just
2607+ wrote the last pixel on this destination scanline: */
2608+ if (!dst_packed
2609+ && (dst_x += 1) == dst_width) {
2610+
2611+ /* calculate the number of bits between the
2612+ last bit of the last pixel and the first bit
2613+ of the first displayed pixel on the next
2614+ scanline. this is equal to the number of
2615+ pad bits plus bits for undisplayed pixels: */
2616+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2617+
2618+ /* while there are bits to shift: */
2619+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2620+
2621+ /* shift the destination primary FIFO: */
2622+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2623+ dst_fifo0,
2624+ dst_fifo0_next,
2625+ dst_fifo0_bits,
2626+ TME_MIN(dst_off, 32),
2627+ dst_raw0,
2628+ dst_order);
2629+ }
2630+
2631+ /* we are now on the first pixel of the next scanline: */
2632+ dst_x = 0;
2633+ }
2634+
2635+ /* shift the destination primary FIFO: */
2636+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2637+ dst_fifo0,
2638+ dst_fifo0_next,
2639+ dst_fifo0_bits,
2640+ 32,
2641+ dst_raw0,
2642+ dst_order);
2643+
2644+ /* iter #20 */
2645+
2646+ /* get a pixel from the source primary FIFO: */
2647+ pixel =
2648+ ((src_fifo0
2649+ >> (src_order == TME_ENDIAN_BIG
2650+ ? (32 - (src_bipp + (20 * src_bipp)))
2651+ : (20 * src_bipp))));
2652+
2653+ /* since source pixels are known at compile time to
2654+ not have subfields, map the source pixel into the
2655+ destination pixel: */
2656+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2657+
2658+ /* if the source buffer is not packed, and we just
2659+ read the last pixel on this source scanline: */
2660+ if (!src_packed
2661+ && ++src_x == src_width) {
2662+
2663+ /* calculate the number of bits between the
2664+ last bit of the last pixel and the first bit
2665+ of the first displayed pixel on the next
2666+ scanline. this is equal to the number of
2667+ pad bits plus bits for undisplayed pixels: */
2668+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2669+
2670+ /* while there are bits to shift: */
2671+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2672+
2673+ /* shift the source primary FIFO: */
2674+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2675+ src_fifo0,
2676+ src_fifo0_next,
2677+ src_fifo0_bits,
2678+ TME_MIN(src_off, 32),
2679+ src_raw0,
2680+ src_order);
2681+ }
2682+
2683+ /* we are now on the first pixel of the next scanline: */
2684+ src_x = 0;
2685+ }
2686+
2687+ /* put the pixel into the destination primary FIFO: */
2688+ dst_fifo0 |=
2689+ (pixel
2690+ << (dst_order == TME_ENDIAN_BIG
2691+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2692+ : (0 * dst_bipp)));
2693+
2694+ /* if the destination buffer is not packed, and we just
2695+ wrote the last pixel on this destination scanline: */
2696+ if (!dst_packed
2697+ && (dst_x += 1) == dst_width) {
2698+
2699+ /* calculate the number of bits between the
2700+ last bit of the last pixel and the first bit
2701+ of the first displayed pixel on the next
2702+ scanline. this is equal to the number of
2703+ pad bits plus bits for undisplayed pixels: */
2704+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2705+
2706+ /* while there are bits to shift: */
2707+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2708+
2709+ /* shift the destination primary FIFO: */
2710+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2711+ dst_fifo0,
2712+ dst_fifo0_next,
2713+ dst_fifo0_bits,
2714+ TME_MIN(dst_off, 32),
2715+ dst_raw0,
2716+ dst_order);
2717+ }
2718+
2719+ /* we are now on the first pixel of the next scanline: */
2720+ dst_x = 0;
2721+ }
2722+
2723+ /* shift the destination primary FIFO: */
2724+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2725+ dst_fifo0,
2726+ dst_fifo0_next,
2727+ dst_fifo0_bits,
2728+ 32,
2729+ dst_raw0,
2730+ dst_order);
2731+
2732+ /* iter #21 */
2733+
2734+ /* get a pixel from the source primary FIFO: */
2735+ pixel =
2736+ ((src_fifo0
2737+ >> (src_order == TME_ENDIAN_BIG
2738+ ? (32 - (src_bipp + (21 * src_bipp)))
2739+ : (21 * src_bipp))));
2740+
2741+ /* since source pixels are known at compile time to
2742+ not have subfields, map the source pixel into the
2743+ destination pixel: */
2744+ pixel = dst->tme_fb_connection_map_pixel[pixel & src_mask];
2745+
2746+ /* if the source buffer is not packed, and we just
2747+ read the last pixel on this source scanline: */
2748+ if (!src_packed
2749+ && ++src_x == src_width) {
2750+
2751+ /* calculate the number of bits between the
2752+ last bit of the last pixel and the first bit
2753+ of the first displayed pixel on the next
2754+ scanline. this is equal to the number of
2755+ pad bits plus bits for undisplayed pixels: */
2756+ src_off = ((src_bypl * 8) - (src_width * src_bipp));
2757+
2758+ /* while there are bits to shift: */
2759+ for (; src_off > 0; src_off -= TME_MIN(src_off, 32)) {
2760+
2761+ /* shift the source primary FIFO: */
2762+ TME_FB_XLAT_SHIFT_SRC(src_fifo0_may_be_unaligned,
2763+ src_fifo0,
2764+ src_fifo0_next,
2765+ src_fifo0_bits,
2766+ TME_MIN(src_off, 32),
2767+ src_raw0,
2768+ src_order);
2769+ }
2770+
2771+ /* we are now on the first pixel of the next scanline: */
2772+ src_x = 0;
2773+ }
2774+
2775+ /* put the pixel into the destination primary FIFO: */
2776+ dst_fifo0 |=
2777+ (pixel
2778+ << (dst_order == TME_ENDIAN_BIG
2779+ ? ((32 - dst_bipp) - (0 * dst_bipp))
2780+ : (0 * dst_bipp)));
2781+
2782+ /* if the destination buffer is not packed, and we just
2783+ wrote the last pixel on this destination scanline: */
2784+ if (!dst_packed
2785+ && (dst_x += 1) == dst_width) {
2786+
2787+ /* calculate the number of bits between the
2788+ last bit of the last pixel and the first bit
2789+ of the first displayed pixel on the next
2790+ scanline. this is equal to the number of
2791+ pad bits plus bits for undisplayed pixels: */
2792+ dst_off = ((dst_bypl * 8) - (dst_width * dst_bipp));
2793+
2794+ /* while there are bits to shift: */
2795+ for (; dst_off > 0; dst_off -= TME_MIN(dst_off, 32)) {
2796+
2797+ /* shift the destination primary FIFO: */
2798+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2799+ dst_fifo0,
2800+ dst_fifo0_next,
2801+ dst_fifo0_bits,
2802+ TME_MIN(dst_off, 32),
2803+ dst_raw0,
2804+ dst_order);
2805+ }
2806+
2807+ /* we are now on the first pixel of the next scanline: */
2808+ dst_x = 0;
2809+ }
2810+
2811+ /* shift the destination primary FIFO: */
2812+ TME_FB_XLAT_SHIFT_DST(dst_fifo0_may_be_unaligned,
2813+