(empty log message)
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -44,7 +44,7 @@ | ||
44 | 44 | * @brief Enables the ADC subsystem. |
45 | 45 | */ |
46 | 46 | #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) |
47 | -#define HAL_USE_ADC TRUE | |
47 | +#define HAL_USE_ADC FALSE | |
48 | 48 | #endif |
49 | 49 | |
50 | 50 | /** |
@@ -50,7 +50,7 @@ | ||
50 | 50 | #define STM32_PLLSRC STM32_PLLSRC_HSI16 |
51 | 51 | #define STM32_PLLM_VALUE 2 |
52 | 52 | #define STM32_PLLN_VALUE 16 |
53 | -#define STM32_PLLP_VALUE 4 | |
53 | +#define STM32_PLLP_VALUE 2 | |
54 | 54 | #define STM32_PLLQ_VALUE 4 |
55 | 55 | #define STM32_PLLR_VALUE 2 |
56 | 56 | #define STM32_HPRE STM32_HPRE_DIV1 |
@@ -108,7 +108,7 @@ | ||
108 | 108 | #define STM32_ADC_ADC1_DMA_PRIORITY 2 |
109 | 109 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 |
110 | 110 | #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
111 | -#define STM32_ADC_PRESCALER_VALUE 1 | |
111 | +#define STM32_ADC_PRESCALER_VALUE 2 | |
112 | 112 | |
113 | 113 | /* |
114 | 114 | * DAC driver system settings. |
@@ -134,6 +134,7 @@ | ||
134 | 134 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
135 | 135 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
136 | 136 | #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
137 | +#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2 | |
137 | 138 | |
138 | 139 | /* |
139 | 140 | * CAN driver system settings. |
@@ -155,6 +155,8 @@ | ||
155 | 155 | #define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5 |
156 | 156 | #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
157 | 157 | #define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
158 | +#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2 | |
159 | +#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2 | |
158 | 160 | |
159 | 161 | /* |
160 | 162 | * CAN driver system settings. |
@@ -125,6 +125,7 @@ | ||
125 | 125 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
126 | 126 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
127 | 127 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
128 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
128 | 129 | |
129 | 130 | /* |
130 | 131 | * CAN driver system settings. |
@@ -130,6 +130,7 @@ | ||
130 | 130 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
131 | 131 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
132 | 132 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
133 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
133 | 134 | |
134 | 135 | /* |
135 | 136 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -152,6 +152,7 @@ | ||
152 | 152 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
153 | 153 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
154 | 154 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
155 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
155 | 156 | |
156 | 157 | /* |
157 | 158 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -58,6 +58,23 @@ | ||
58 | 58 | /*===========================================================================*/ |
59 | 59 | |
60 | 60 | /** |
61 | + * @brief ADC voltage regulator enable. | |
62 | + * | |
63 | + * @param[in] adc pointer to the ADC registers block | |
64 | + */ | |
65 | +NOINLINE static void adc_lld_vreg_on(ADC_TypeDef *adc) { | |
66 | + volatile uint32_t loop; | |
67 | + | |
68 | + osalDbgAssert(adc->CR == 0, "invalid register state"); | |
69 | + | |
70 | + adc->CR = ADC_CR_ADVREGEN; | |
71 | + loop = (STM32_HCLK >> 20) << 4; | |
72 | + do { | |
73 | + loop--; | |
74 | + } while (loop > 0); | |
75 | +} | |
76 | + | |
77 | +/** | |
61 | 78 | * @brief Stops an ongoing conversion, if any. |
62 | 79 | * |
63 | 80 | * @param[in] adc pointer to the ADC registers block |
@@ -167,11 +184,13 @@ | ||
167 | 184 | ADC->CCR = 0; |
168 | 185 | #endif |
169 | 186 | |
170 | - osalDbgAssert(ADC1->CR == 0, "invalid register state"); | |
187 | + /* Regulator enabled and stabilized before calibration.*/ | |
188 | + adc_lld_vreg_on(ADC1); | |
189 | + | |
171 | 190 | ADC1->CR |= ADC_CR_ADCAL; |
172 | - osalDbgAssert(ADC1->CR != 0, "invalid register state"); | |
173 | 191 | while (ADC1->CR & ADC_CR_ADCAL) |
174 | 192 | ; |
193 | + ADC1->CR = 0; | |
175 | 194 | rccDisableADC1(); |
176 | 195 | } |
177 | 196 |
@@ -206,6 +225,9 @@ | ||
206 | 225 | } |
207 | 226 | #endif /* STM32_ADC_USE_ADC1 */ |
208 | 227 | |
228 | + /* Regulator enabled and stabilized before calibration.*/ | |
229 | + adc_lld_vreg_on(ADC1); | |
230 | + | |
209 | 231 | /* ADC initial setup, starting the analog part here in order to reduce |
210 | 232 | the latency when starting a conversion.*/ |
211 | 233 | adcp->adc->CR = ADC_CR_ADEN; |
@@ -244,6 +266,9 @@ | ||
244 | 266 | ; |
245 | 267 | } |
246 | 268 | |
269 | + /* Regulator and anything else off.*/ | |
270 | + adcp->adc->CR = 0; | |
271 | + | |
247 | 272 | #if STM32_ADC_USE_ADC1 |
248 | 273 | if (&ADCD1 == adcp) |
249 | 274 | rccDisableADC1(); |
@@ -161,7 +161,7 @@ | ||
161 | 161 | * default, @p STM32_ADC_CKMODE_ADCCLK). |
162 | 162 | */ |
163 | 163 | #if !defined(STM32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__) |
164 | -#define STM32_ADC_PRESCALER_VALUE 1 | |
164 | +#define STM32_ADC_PRESCALER_VALUE 2 | |
165 | 165 | #endif |
166 | 166 | #endif |
167 | 167 |
@@ -188,6 +188,10 @@ | ||
188 | 188 | #error "STM32_HAS_ADC1 not defined in registry" |
189 | 189 | #endif |
190 | 190 | |
191 | +#if !defined(STM32_ADC_SUPPORTS_PRESCALER) | |
192 | +#error "STM32_ADC_SUPPORTS_PRESCALER not defined in registry" | |
193 | +#endif | |
194 | + | |
191 | 195 | #if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_HANDLER)) |
192 | 196 | #error "STM32_ADC1_HANDLER not defined in registry" |
193 | 197 | #endif |
@@ -246,9 +250,7 @@ | ||
246 | 250 | |
247 | 251 | /* ADC clock source checks.*/ |
248 | 252 | #if STM32_ADC_SUPPORTS_PRESCALER == TRUE |
249 | -#if STM32_ADC_PRESCALER_VALUE == 1 | |
250 | -#define STM32_ADC_PRESC 0U | |
251 | -#elif STM32_ADC_PRESCALER_VALUE == 2 | |
253 | +#if STM32_ADC_PRESCALER_VALUE == 2 | |
252 | 254 | #define STM32_ADC_PRESC 1U |
253 | 255 | #elif STM32_ADC_PRESCALER_VALUE == 4 |
254 | 256 | #define STM32_ADC_PRESC 2U |
@@ -264,7 +264,7 @@ | ||
264 | 264 | #define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U) |
265 | 265 | |
266 | 266 | #define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */ |
267 | -#define STM32_ADCSEL_NOCLK (0U << 30U) /**< ADC source is SYSCLK. */ | |
267 | +#define STM32_ADCSEL_SYSCLK (0U << 30U) /**< ADC source is SYSCLK. */ | |
268 | 268 | #define STM32_ADCSEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */ |
269 | 269 | #define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */ |
270 | 270 | /** @} */ |
@@ -402,7 +402,7 @@ | ||
402 | 402 | * @note The allowed values are 2..32. |
403 | 403 | */ |
404 | 404 | #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) |
405 | -#define STM32_PLLP_VALUE 4 | |
405 | +#define STM32_PLLP_VALUE 2 | |
406 | 406 | #endif |
407 | 407 | |
408 | 408 | /** |
@@ -1463,8 +1463,8 @@ | ||
1463 | 1463 | /** |
1464 | 1464 | * @brief ADC clock frequency. |
1465 | 1465 | */ |
1466 | -#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__) | |
1467 | -#define STM32_ADCCLK 0 | |
1466 | +#if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__) | |
1467 | +#define STM32_ADCCLK STM32_SYSCLK | |
1468 | 1468 | #elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK |
1469 | 1469 | #define STM32_ADCCLK STM32_PLL_P_CLKOUT |
1470 | 1470 | #elif STM32_ADCSEL == STM32_ADCSEL_HSI16 |
@@ -51,13 +51,13 @@ | ||
51 | 51 | */ |
52 | 52 | #if defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \ |
53 | 53 | defined(__DOXYGEN__) |
54 | -#define PLATFORM_NAME "STM32G04 Access Line" | |
54 | +#define PLATFORM_NAME "STM32G4 Access Line" | |
55 | 55 | |
56 | 56 | #elif defined(STM32G473xx) |
57 | -#define PLATFORM_NAME "STM32G0 Performance Line" | |
57 | +#define PLATFORM_NAME "STM32G4 Performance Line" | |
58 | 58 | |
59 | 59 | #elif defined(STM32G483xx) |
60 | -#define PLATFORM_NAME "STM32G0 Performance Line with Crypto" | |
60 | +#define PLATFORM_NAME "STM32G4 Performance Line with Crypto" | |
61 | 61 | |
62 | 62 | #elif defined(STM32G474xx) |
63 | 63 | #define PLATFORM_NAME "STM32G4 Hi-resolution Line" |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -50,7 +50,7 @@ | ||
50 | 50 | #define STM32_PLLSRC STM32_PLLSRC_HSI16 |
51 | 51 | #define STM32_PLLM_VALUE 2 |
52 | 52 | #define STM32_PLLN_VALUE 16 |
53 | -#define STM32_PLLP_VALUE 4 | |
53 | +#define STM32_PLLP_VALUE 2 | |
54 | 54 | #define STM32_PLLQ_VALUE 4 |
55 | 55 | #define STM32_PLLR_VALUE 2 |
56 | 56 | #define STM32_HPRE STM32_HPRE_DIV1 |
@@ -108,7 +108,7 @@ | ||
108 | 108 | #define STM32_ADC_ADC1_DMA_PRIORITY 2 |
109 | 109 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 |
110 | 110 | #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
111 | -#define STM32_ADC_PRESCALER_VALUE 1 | |
111 | +#define STM32_ADC_PRESCALER_VALUE 2 | |
112 | 112 | |
113 | 113 | /* |
114 | 114 | * DAC driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -155,6 +155,8 @@ | ||
155 | 155 | #define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5 |
156 | 156 | #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
157 | 157 | #define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 |
158 | +#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2 | |
159 | +#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2 | |
158 | 160 | |
159 | 161 | /* |
160 | 162 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |
@@ -149,6 +149,7 @@ | ||
149 | 149 | #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 |
150 | 150 | #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 |
151 | 151 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 |
152 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
152 | 153 | |
153 | 154 | /* |
154 | 155 | * CAN driver system settings. |
@@ -157,6 +157,7 @@ | ||
157 | 157 | #define STM32_ADC_ADC12_IRQ_PRIORITY 5 |
158 | 158 | #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 |
159 | 159 | #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2 |
160 | +#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2 | |
160 | 161 | |
161 | 162 | /* |
162 | 163 | * CAN driver system settings. |