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hardware/intel/intel-driver


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99075c5 2014-06-16 12:53:35 Gwenole Beauchesne

decoder: h264: don't deallocate surface storage of older frames.

Drop the optimization whereby surfaces that are no longer marked as
reference and that were already displayed are to be destroyed. This
is wrong mainly for two reasons:

1. The surface was displayed... once but it may still be needed for
subsequent operations like displaying it again, using it for a
transcode pipeline (encode) for instance, etc.

2. The new set of ReferenceFrames[] correspond to the active set of
reference frames used for decoding the current slice. In presence
of Multiview Coding (MVC), that could correspond to the current
view, in view order index, but the surface may still be needed
for decoding the next view with the same view_id, while also
decoding other views with another set of reference frames for them.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 77af916b44da04e3424490506a7e5bef39c80c7c)

1ae22a0 2014-06-16 12:53:35 Li Xiaowei

encoder: MVC: Add support for MVC profiles

This is a part of bd630edd844b88ea543a027654db296ff7da16cd on staging

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

40af27d 2014-06-16 12:53:35 Li Xiaowei

MVC: CODEC_H264_MVC defination and relatived properties check

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit 7d1ddfd3646f35f306f38bfabef6af9b2ebb19f4)

Conflicts:
src/i965_drv_video.c

ab9de41 2014-06-16 12:53:34 Gwenole Beauchesne

h264: Add the macros for MVC profiles to keep backward compatibility with libva 1.3.1

It is a part of 1f244834dedb7b46863b315a898d8649d01c5f58 on staging

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

8715ce3 2014-06-16 12:53:34 Zhao Yakui

Define i965_CreateSurfaces in header file explicitly to avoid multiple declaration

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 8b3945aa5df443e93a3f5e6e97dffb1574e2a936)

89dcd2e 2014-06-16 12:53:34 Xiang, Haihao

Check the pointer against NULL

The issue is reported by Klockwork

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 80d1f89388c9cb70218cd759592d2167c8845322)

ce2cc4e 2014-06-16 11:27:12 Xiang, Haihao

1.3.3.pre1 for development

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

cc40368 2014-06-16 11:21:07 Xiang, Haihao

Intel driver 1.3.2

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

5e89ef4 2014-06-09 17:17:36 Zhao, Yakui

Encoding: Fix one type error in intra-prediction shader on BDW

Otherwise it will cause the incorrect intra-prediction for encoding on
Broadwell.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit 20bee4c3cb478702155df1779f24ec483aeab059)

364d9b1 2014-06-09 12:56:22 Xiang, Haihao

Update NEWS for 1.3.2 pre1

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

9047420 2014-06-06 13:52:23 Zhao, Halley

debug: add g_intel_debug_option_flags for simple driver debug

VA_INTEL_DEBUG_ASSERT decides assert() is enabled or not
VA_INTEL_DEBUG_BENCH decides skipping swapbuffer in dri output
(cherry picked from commit 60413182f66c44781456e827b439e98f21cfae4c)

aa1b177 2014-06-06 13:49:01 Xiang, Haihao

Fix the scaling issue on IVB/HSW/BDW

Scaling is done on each 16x16 block. The shader for scaling
might write pixels out-of-rectangle if the rectangle width/height
isn't aligned to 16.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit d560387cc819a31791c2a30026473c9bd8786f07)

05dbef1 2014-06-06 13:48:30 Xiang, Haihao

VPP: Simplify surface state setting for csc and scaling on IVB/HSW/BDW

v2: bpp[] is in unit of bits

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit d415357f25fc01b96592ba29ba95da9d6dc82ff3)

c39d208 2014-06-06 13:47:55 Xiang, Haihao

New structure i965_fourcc_info

and hold all supported fourcc in an array

v2: bpp[] in bit and fix the vertical factor for 411P (Yakui)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 1de3a2cdc8c3f8b2f6191c0f114fa1167f40f2ec)

Conflicts:

src/i965_drv_video.c

b44240a 2014-06-06 13:46:06 Xiang, Haihao

mpeg2: calculate the slice data length on IVB

Sometimes pending datas are added in slice data buffer, however
HW requires slice data length excludes pending datas, otherwise
the behavior is undefined

https://bugs.freedesktop.org/show_bug.cgi?id=77041

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit a9004e6c5c7f33cd1e33e4dab92a5a0017714bbd)

dfffd00 2014-06-06 13:45:21 Sebastian Ramacher

Propagate error code

Signed-off-by: Sebastian Ramacher <sramacher@debian.org>
Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com>
(cherry picked from commit ca1acd54eb59eadabfb40a4b61df2e8968b5e00d)

a664a09 2014-06-06 13:45:03 Sebastian Ramacher

Define i965_proc_picture in header

Signed-off-by: Sebastian Ramacher <sramacher@debian.org>
Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com>
(cherry picked from commit e9e9b55c769a6c0b90d6af5d89a6baf4c6f742be)

338180c 2014-06-06 13:44:34 Xiang, Haihao

VPP: MADI on SNB

Set the right surface states for reference, STMM and output surface,
fix the shader as well

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-By: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
(cherry picked from commit 1d1b8da1284f7f918733db79428f09af38d7e14a)

Conflicts:

src/i965_post_processing.c

f07cd58 2014-06-06 13:40:44 Xiang, Haihao

VPP: i965_vpp_clear_surface() is still used for CSC on BDW

https://bugs.freedesktop.org/show_bug.cgi?id=79065

The regression is caused by commit 42258e1

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 0523c58148e9496927f2c3fa9a641885a0350d0f)

7465b16 2014-06-06 13:26:43 Xiang, Haihao

Remove unnecessary check with IS_GEN8()

It is always true or false

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 42258e128f19b93aa102672d5f61eb73d9f9808f)

60ea472 2014-06-05 17:27:32 Gwenole Beauchesne

decoder: h264: don't allocate bottom DMV buffer on Broadwell.

Broadwell now uses a unique DMV buffer, irrespective of any field
coding mode. The dmv_buffer is not used, so it doesn't need to be
allocated at all.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

628c958 2014-06-05 17:27:26 Gwenole Beauchesne

decoder: h264: only allocate tiled surfaces for Sandybridge an newer.

Don't allocate tiled surfaces on Ironlake platforms and earlier, stick
to linear surfaces.

This is a regression from 6d76944.

Reported-by: Haihao Xiang <haihao.xiang@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

e9c2a67 2014-06-03 02:30:43 Gwenole Beauchesne

decoder: h264: optimize support for grayscale surfaces.

Optimize support for grayscale surfaces in two aspects: (i) space
by only allocating the luminance component ; (ii) speed by avoiding
initialization of the (now inexistent) chrominance planes.

Keep backward compatibility with older codec layers that only
supported YUV 4:2:0 and not grayscale formats properly.

v2: fix check for extra H.264 chroma formats [Haihao]

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

6d76944 2014-06-03 02:30:43 Gwenole Beauchesne

decoder: h264: factor out allocation of reconstructed surfaces.

Add new avc_ensure_surface_bo() helper function to factor out the
allocatiion and initialization processes of the reconstructed VA
surface buffer stores.

Keep preferred native format (NV12) and initialize chroma values
to 0.0 (0x80) when needed for "fake" grayscale (Y800) surfaces
implemented on top of existing NV12.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

e29345c 2014-06-03 02:30:43 Gwenole Beauchesne

config: fix supported set of chroma formats for JPEG decode.

If the hardware supports JPEG decoding, then we have to expose the
right set of chroma formats for the output (decoded) VA surface. In
particular, we could support YUV 4:0:0, 4:1:0, 4:2:2 and 4:4:4.

v2: export support for YUV 4:0:0 (grayscale) too [Haihao]

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

9200fe2 2014-06-03 02:30:43 Gwenole Beauchesne

config: fix vaCreateConfig() to not override user chroma format.

Only validate the user-defined chroma format (VAConfigAttribRTFormat)
attribute, if any. Don't override it. i.e. append a pre-defined value
only if it was not defined by the user beforehand.

Propertly return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT if the supplied
chroma format is not supported.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

0f2e2a9 2014-06-03 02:30:43 Gwenole Beauchesne

config: fix vaGetConfigAttributes() to validate profile/entrypoint.

Factor out code to validate profile/entrypoint per the underlying
hardware capabilities. Also fix vaGetConfigAttributes() to really
validate the profile/entrypoint pair.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

cffa752 2014-06-03 02:30:43 Gwenole Beauchesne

surface: factor out release of surface buffer storage.

Introduce a new i965_destroy_surface_storage() helper function to
unreference the underlying GEM buffer object, and any associated
private data, if any.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

18d0aee 2014-06-03 02:30:43 Gwenole Beauchesne

surface: fix geometry (size, layout) of grayscale surfaces.

Fix size of the allocated buffer used to represent grayscale (Y800)
surfaces. Only the luminance component is needed, thus implying a
single plane.

Likewise, update render routines to only submit the first plane.
The existing render kernels readily only care about that single
plane.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

3afe051 2014-05-26 13:17:31 Xiang, Haihao

mpeg2: check frame_pred_frame_dct instead of progressive_frame

Some MPEG-2 videos set progressive_frame to 1 and set
frame_pred_frame_dct to 0, which is not conformed to MPEG-2 spec.
bottom field may be used to form prediction if frame_pred_frame_dct is
0. Previously the bottom field is excluded from the frame store list

https://bugs.freedesktop.org/show_bug.cgi?id=73424

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit b3031d16b1ea9ef2ab95bc09e59f0db5214a1125)