Révision | 0a312b85cb433386804a2ca79f4a1f7ab75f64a7 (tree) |
---|---|
l'heure | 2022-01-21 14:52:56 |
Auteur | Yifei Jiang <jiangyifei@huaw...> |
Commiter | Alistair Francis |
target/riscv: Implement function kvm_arch_init_vcpu
Get isa info from kvm while kvm init.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-4-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
@@ -38,6 +38,24 @@ | ||
38 | 38 | #include "qemu/log.h" |
39 | 39 | #include "hw/loader.h" |
40 | 40 | |
41 | +static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, | |
42 | + uint64_t idx) | |
43 | +{ | |
44 | + uint64_t id = KVM_REG_RISCV | type | idx; | |
45 | + | |
46 | + switch (riscv_cpu_mxl(env)) { | |
47 | + case MXL_RV32: | |
48 | + id |= KVM_REG_SIZE_U32; | |
49 | + break; | |
50 | + case MXL_RV64: | |
51 | + id |= KVM_REG_SIZE_U64; | |
52 | + break; | |
53 | + default: | |
54 | + g_assert_not_reached(); | |
55 | + } | |
56 | + return id; | |
57 | +} | |
58 | + | |
41 | 59 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
42 | 60 | KVM_CAP_LAST_INFO |
43 | 61 | }; |
@@ -79,7 +97,21 @@ void kvm_arch_init_irq_routing(KVMState *s) | ||
79 | 97 | |
80 | 98 | int kvm_arch_init_vcpu(CPUState *cs) |
81 | 99 | { |
82 | - return 0; | |
100 | + int ret = 0; | |
101 | + target_ulong isa; | |
102 | + RISCVCPU *cpu = RISCV_CPU(cs); | |
103 | + CPURISCVState *env = &cpu->env; | |
104 | + uint64_t id; | |
105 | + | |
106 | + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, | |
107 | + KVM_REG_RISCV_CONFIG_REG(isa)); | |
108 | + ret = kvm_get_one_reg(cs, id, &isa); | |
109 | + if (ret) { | |
110 | + return ret; | |
111 | + } | |
112 | + env->misa_ext = isa; | |
113 | + | |
114 | + return ret; | |
83 | 115 | } |
84 | 116 | |
85 | 117 | int kvm_arch_msi_data_to_gsi(uint32_t data) |