Commit: 2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9 - qemu (git)

Commit MetaInfo

• Révision: 2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9 (tree)
• l'heure: 2022-01-21 14:52:56
• Auteur: Frank Chang <frank.chang@sifi...>
• Commiter: Alistair Francis

Message de Log

target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

Signed-off-by: Frank Chang <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Message-id: [e-mail]
Signed-off-by: Alistair Francis <[e-mail]>

Change Summary

• modified: target/riscv/cpu.c

Modification

--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -688,6 +688,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+    DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),