Commit: 494104093fafab12208a8f1f0cb2ab5f5c8c7035 - qemu (git)

Commit MetaInfo

• Révision: 494104093fafab12208a8f1f0cb2ab5f5c8c7035 (tree)
• l'heure: 2022-01-21 14:52:56
• Auteur: Frank Chang <frank.chang@sifi...>
• Commiter: Alistair Francis

Message de Log

target/riscv: rvv-1.0: Add Zve64f support for load and store insns

All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.

Signed-off-by: Frank Chang <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Message-id: [e-mail]
Signed-off-by: Alistair Francis <[e-mail]>

Change Summary

• modified: target/riscv/insn_trans/trans_rvv.c.inc

Modification

--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
                                 uint8_t eew)
 {
     int8_t emul = eew - s->sew + s->lmul;
-    return (emul >= -3 && emul <= 3) &&
-            require_align(vs2, emul) &&
-            require_align(vd, s->lmul) &&
-            require_nf(vd, nf, s->lmul);
+    bool ret = (emul >= -3 && emul <= 3) &&
+               require_align(vs2, emul) &&
+               require_align(vd, s->lmul) &&
+               require_nf(vd, nf, s->lmul);
+
+    /*
+     * All Zve* extensions support all vector load and store instructions,
+     * except Zve64* extensions do not support EEW=64 for index values
+     * when XLEN=32. (Section 18.2)
+     */
+    if (get_xl(s) == MXL_RV32) {
+        ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+    }
+
+    return ret;
 }
 
 /*