| Révision | c7a26fb2f6bafd45b983d81d180f624c0e8c4d2b (tree) |
|---|---|
| l'heure | 2022-01-21 14:52:56 |
| Auteur | Frank Chang <frank.chang@sifi...> |
| Commiter | Alistair Francis |
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc (diff)| @@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) | ||
| 129 | 129 | { |
| 130 | 130 | TCGv s1, dst; |
| 131 | 131 | |
| 132 | - if (!require_rvv(s) || !has_ext(s, RVV)) { | |
| 132 | + if (!require_rvv(s) || | |
| 133 | + !(has_ext(s, RVV) || s->ext_zve64f)) { | |
| 133 | 134 | return false; |
| 134 | 135 | } |
| 135 | 136 |
| @@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) | ||
| 164 | 165 | { |
| 165 | 166 | TCGv dst; |
| 166 | 167 | |
| 167 | - if (!require_rvv(s) || !has_ext(s, RVV)) { | |
| 168 | + if (!require_rvv(s) || | |
| 169 | + !(has_ext(s, RVV) || s->ext_zve64f)) { | |
| 168 | 170 | return false; |
| 169 | 171 | } |
| 170 | 172 |
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