Commit: e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf - qemu (git)

Commit MetaInfo

• Révision: e65a5f227d77a5dbae7a7123c3ee915ee4bd80cf (tree)
• l'heure: 2018-07-20 01:07:31
• Auteur: Alex Bennée <alex.bennee@lina...>
• Commiter: Richard Henderson

Message de Log

tcg/aarch64: limit mul_vec size

In AdvSIMD we can only do 32x32 integer multiples although SVE is
capable of larger 64 bit multiples. As a result we can end up
generating invalid opcodes. Fix this by only reprting we can emit
mul vector ops if the size is small enough.

Fixes a crash on:

sve-all-short-v8.3+sve@vq3/insn_mul_z_zi_INC.risu.bin

When running on AArch64 hardware.

Reviewed-by: Richard Henderson <[e-mail]>
Signed-off-by: Alex Bennée <[e-mail]>
Message-Id: <[e-mail]>
[rth: Removed the tcg_debug_assert -- there are plenty of other
cases that we do not diagnose within the insn encoding helpers.]
Signed-off-by: Richard Henderson <[e-mail]>

Change Summary

• modified: tcg/aarch64/tcg-target.inc.c

Modification

--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2219,7 +2219,6 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     switch (opc) {
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
-    case INDEX_op_mul_vec:
     case INDEX_op_and_vec:
     case INDEX_op_or_vec:
     case INDEX_op_xor_vec:
@@ -2232,6 +2231,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
         return 1;
+    case INDEX_op_mul_vec:
+        return vece < MO_64;
 
     default:
         return 0;