Révision | 23387416daa077bf582c38fb56fa8a721d17e21a (tree) |
---|---|
l'heure | 2022-07-26 18:29:02 |
Auteur | Peng Fan <peng.fan@nxp....> |
Commiter | Stefano Babic |
ddr: imx8m: helper: load ddr firmware according to binman symbols
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.
And that could save binary size for many KBs.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
[Alper: Check BINMAN_SYMS_OK instead]
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
@@ -4,6 +4,7 @@ | ||
4 | 4 | */ |
5 | 5 | |
6 | 6 | #include <common.h> |
7 | +#include <binman_sym.h> | |
7 | 8 | #include <log.h> |
8 | 9 | #include <spl.h> |
9 | 10 | #include <asm/global_data.h> |
@@ -24,15 +25,30 @@ DECLARE_GLOBAL_DATA_PTR; | ||
24 | 25 | #define DMEM_OFFSET_ADDR 0x00054000 |
25 | 26 | #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) |
26 | 27 | |
28 | +binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos); | |
29 | +binman_sym_declare(ulong, ddr_1d_imem_fw, size); | |
30 | + | |
31 | +binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos); | |
32 | +binman_sym_declare(ulong, ddr_1d_dmem_fw, size); | |
33 | + | |
34 | +#if !IS_ENABLED(CONFIG_IMX8M_DDR3L) | |
35 | +binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos); | |
36 | +binman_sym_declare(ulong, ddr_2d_imem_fw, size); | |
37 | + | |
38 | +binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos); | |
39 | +binman_sym_declare(ulong, ddr_2d_dmem_fw, size); | |
40 | +#endif | |
41 | + | |
27 | 42 | /* We need PHY iMEM PHY is 32KB padded */ |
28 | 43 | void ddr_load_train_firmware(enum fw_type type) |
29 | 44 | { |
30 | 45 | u32 tmp32, i; |
31 | 46 | u32 error = 0; |
32 | 47 | unsigned long pr_to32, pr_from32; |
33 | - unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; | |
48 | + uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0; | |
34 | 49 | unsigned long imem_start = (unsigned long)&_end + fw_offset; |
35 | 50 | unsigned long dmem_start; |
51 | + unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN; | |
36 | 52 | |
37 | 53 | #ifdef CONFIG_SPL_OF_CONTROL |
38 | 54 | if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { |
@@ -42,11 +58,30 @@ void ddr_load_train_firmware(enum fw_type type) | ||
42 | 58 | } |
43 | 59 | #endif |
44 | 60 | |
45 | - dmem_start = imem_start + IMEM_LEN; | |
61 | + dmem_start = imem_start + imem_len; | |
62 | + | |
63 | + if (BINMAN_SYMS_OK) { | |
64 | + switch (type) { | |
65 | + case FW_1D_IMAGE: | |
66 | + imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos); | |
67 | + imem_len = binman_sym(ulong, ddr_1d_imem_fw, size); | |
68 | + dmem_start = binman_sym(ulong, ddr_1d_dmem_fw, image_pos); | |
69 | + dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size); | |
70 | + break; | |
71 | + case FW_2D_IMAGE: | |
72 | +#if !IS_ENABLED(CONFIG_IMX8M_DDR3L) | |
73 | + imem_start = binman_sym(ulong, ddr_2d_imem_fw, image_pos); | |
74 | + imem_len = binman_sym(ulong, ddr_2d_imem_fw, size); | |
75 | + dmem_start = binman_sym(ulong, ddr_2d_dmem_fw, image_pos); | |
76 | + dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size); | |
77 | +#endif | |
78 | + break; | |
79 | + } | |
80 | + } | |
46 | 81 | |
47 | 82 | pr_from32 = imem_start; |
48 | 83 | pr_to32 = IMEM_OFFSET_ADDR; |
49 | - for (i = 0x0; i < IMEM_LEN; ) { | |
84 | + for (i = 0x0; i < imem_len; ) { | |
50 | 85 | tmp32 = readl(pr_from32); |
51 | 86 | writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); |
52 | 87 | pr_to32 += 1; |
@@ -59,7 +94,7 @@ void ddr_load_train_firmware(enum fw_type type) | ||
59 | 94 | |
60 | 95 | pr_from32 = dmem_start; |
61 | 96 | pr_to32 = DMEM_OFFSET_ADDR; |
62 | - for (i = 0x0; i < DMEM_LEN; ) { | |
97 | + for (i = 0x0; i < dmem_len; ) { | |
63 | 98 | tmp32 = readl(pr_from32); |
64 | 99 | writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); |
65 | 100 | pr_to32 += 1; |
@@ -73,7 +108,7 @@ void ddr_load_train_firmware(enum fw_type type) | ||
73 | 108 | debug("check ddr_pmu_train_imem code\n"); |
74 | 109 | pr_from32 = imem_start; |
75 | 110 | pr_to32 = IMEM_OFFSET_ADDR; |
76 | - for (i = 0x0; i < IMEM_LEN; ) { | |
111 | + for (i = 0x0; i < imem_len; ) { | |
77 | 112 | tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); |
78 | 113 | pr_to32 += 1; |
79 | 114 | tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + |
@@ -95,7 +130,7 @@ void ddr_load_train_firmware(enum fw_type type) | ||
95 | 130 | debug("check ddr4_pmu_train_dmem code\n"); |
96 | 131 | pr_from32 = dmem_start; |
97 | 132 | pr_to32 = DMEM_OFFSET_ADDR; |
98 | - for (i = 0x0; i < DMEM_LEN;) { | |
133 | + for (i = 0x0; i < dmem_len;) { | |
99 | 134 | tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); |
100 | 135 | pr_to32 += 1; |
101 | 136 | tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + |