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Description du projet

GPL Cver is a full Verilog HDL IEEE P1364 standard
simulator. It is a high capacity commercial
quality interpretive Verilog simulator. Full
support for all three PLI interfaces is included:
tf_, acc_, and vpi_. Some Verilog 2001 features
are supported.

Système requise

System requirement is not defined
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2004-03-03 20:41 Retour à la liste release
1.10g

Il ya maintenant un makefile pour Cygwin, et PLI travaille avec Cygwin release 1.55 et antérieures. Le code du paramètre a été réécrit pour correspondre à XL pour les deux livres et defparams.
Tags: Minor bugfixes
There is now a makefile for Cygwin, and PLI works with Cygwin release 1.55 and earlier. The parameter code has been rewritten to match XL for both pound and defparams.

Project Resources