Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
Open source project that offer summary and download services on this page is a project that carry out their development work on other open source development sites. Their work is linked to this page via a feature called OFI, and their work is not carried out here on OSDN site.
